This documentation was automatically generated from the Markdown file README.md in the Git repository https://git.gsi.de/BEA_HDL/Cryring_BPM_Gateware
Any changes should be applied to the Markdown file, which can be converted to DokuWiki format using the script FPGA_Common/doc/scripts/create_dokuwiki.py.

The documentation is also available as a PDF: Cryring_BPM_Gateware_Documentation.pdf

An up to date PDF version can be downloaded from the CI/CD section: https://git.gsi.de/BEA_HDL/Cryring_BPM_Gateware/-/pipelines.

Documentation that is common to multiple FPGA based projects can be found here: FPGA Common Documentation. It is also available as a PDF: FPGA_Common_Documentation.pdf

The code of this project and also the source of this documentation are under version control in a Git repository whose upstream is:
https://git.gsi.de/BEA_HDL/Cryring_BPM_Gateware
The relevant branch is master.

Additional datasheets and papers are included as a Git submodule of the main Git repository. The upstream of the submodule is:
https://git.gsi.de/BEA_HDL/datasheets
The relevant branch is master.

Common code is included as a Git submodule of the main Git repository. The upstream of the submodule is:
https://git.gsi.de/BEA_HDL/FPGA_Common
The relevant branch is master.

Installation scripts to set up a Gitlab runner for continuous integration including all necessary software to build the gateware can be found in a Git repository whose upstream is:
https://git.gsi.de/BEA_HDL/Gitlab_Runner_Setup_Centos_7
The relevant branch is master.

This document describes the gateware (= FPGA firmware) implementation of the Beam Position Monitor (BPM) for the Cryring accelerator at GSI. The term Trajectory Measurement System (TMS) is also common for this system and is used as a synonym for BPM. The BPM measures the horizontal and vertical beam positions at nine places of the accelerator ring, resulting in 18 location results.

There had been a previous implementation by Piotr Miedzik, but since no documentation could be found besides a conference paper [2], it was decided to reimplement the gateware.

At each of the 18 measurement spots two capacitor plates are used to detect the electrostatic induction of the passing by charged particle bunches.

Figure 1.1: Mechanical drawing of a single BPM. The two segments of the slotted tube are the capacitor plates. The box on the top is the amplifier. Image origin: [3]

The 36 voltages of the capacitor plates are amplified and led via coaxial cables to a single evaluation point where the analog to digital conversion and the digital processing takes place.

Figure 1.2: Cryring BPM system overview. This document only describes the implementation of the block labeled 125 MSa/s ADC DAQ System (36 ch.), excluding the software part. Image origin: [3]

The positions of the particle beam are calculated respectively from the voltage difference of two related capacitor plates using the algorithm described in chapter 2.

Figure 1.3: Schematic of the digital input filters. Image origin: Andreas Reiter

The moving average filter is intended to reduce the noise when higher frequencies are not of interest.

The Chebyshev filter is intended to suppress a 70 kHz noise on certain BPMs, which couples in from the supply voltage of the ion getter pumps.

Figure 1.4: Frequency response of the Chebyshev filter

Each of the 36 voltages coming from the amplifiers at the capacitor plates is sampled by a Renesas ISLA216P ADC at a sampling rate of 125 MHz with a resolution of 16 bits. Respectively four of the ADCs are placed on a single FMC board. Respectively two (ore only one for the last one) of the FMC boards are mounted on an AFC carrier board which is equipped with a Xilinx Artix XC7A200T FPGA for data processing [4].

Figure 1.5: An AFC carrier board with two mounted ADC FMC boards. The FPGA is located under the blue heat spreader.

The FPGA is a mid-range device providing the following resources [5]:

• Logic cells: 215,360
• Block RAMs: 365 x 36 Kibits
• Multipliers/Adders: 740

The whole system uses five AFC carrier boards which are mounted in a MicroTCA crate together with a timing receiver and a FEC for post processing. Each of the five FPGAs is responsible for the processing of up to eight ADC data streams. The communication between the FEC and the FPGAs takes place via PCI Express over the so called backplane of the MicroTCA crate.

Figure 1.6: MicroTCA crate with from left to right: power supply, MCH, FEC, timing receiver, 5 AFC boards with 9 mounted FMC ADC boards, second MCH

This document describes the gatewares of the FPGAs on the five AFC carrier boards. The gatewares are identical independent of the number of mounted FMC boards.

The beam position is calculated from the measurement of the voltages of two corresponding plates:

with

and

where is a proportionality factor influenced by the dimension of the measurement system, some possible voltage offset and the beam position.

The capacitance of the two corresponding capacitor plates can differ from their nominal value so that one of the voltages has to be corrected by multiplying a correction factor:

The default value of in the gateware is 1. It is configurable by the software via register accesses.

A linear least squares approach is used to reduce measurement errors. The choice of the algorithm is described in [1]. The optimal approach would be an orthogonal least squares algorithm. Since the relative error of the difference signal dominates that of the sum signal , it can be simplified to a vertical least squares algorithm:

Minimizing

via partial differentiation

and

leads to

Equation 2.10: BPM algorithm

The variance of the least squares algorithm result is calculated as follows:

The beam intensity is calculated as follows:

For further reducing the data rate and reducing the measurement noise, the result of the least squares algorithm is averaged over an adjustable number of samples . This is implemented via a simple block averaging:

The variance of the averaging result is calculated by averaging the variances and dividing by the averaging length:

The average intensity is calculated as follows:

There is an input signal coming from a timing receiver that gates the calculation of the least squares algorithm. By default, the gateware is configured to use the first MLVDS line as an input for the gate signal. A calculation will start with the low to high transition of the gate signal and will be repeated continuously until a high to low transition is detected, after which the current calculation will still be completed.

The RF pulse signal is intended to synchronize the calculation of the least squares algorithm with the frequency of the particle bunches. A possible previous calculation of the least squares algorithm will be finished and a new calculation will be started whenever a RF pulse is detected.

This parameter defines the number of ADC samples that will be taken into account by the least squares algorithm if no RF pulses are present. The detection of a RF pulse will override this parameter. The overriding will only work as expected if the calculation length is set to a value that is longer than the period of the RF pulses.

The available range of values for the calculation length is 3 to 65536.

This parameter defines the number of least squares algorithm results that will be taken into account by the averaging algorithm.

The available range of values for the averaging length is 1 to 1048576.

This project incorporates the code from the FPGA_Common Git repository which is used in multiple projects. The documentation of the common features can be found here:

Documentation about the register bank, the architecture information storage and the observer can be found here:
https://git.gsi.de/BEA_HDL/FPGA_Common#2-common-monitoring-and-control-features

There is a expert GUI that can be used together with multiple projects:
https://git.gsi.de/BEA_HDL/FPGA_Common#3-fpga-observer

You can find instructions on how to build and simulate the gateware here:
https://git.gsi.de/BEA_HDL/FPGA_Common#4-build-flow-and-simulation

You can find usefull scripts here:
https://git.gsi.de/BEA_HDL/FPGA_Common#5-helper-scripts

Information about the continuous integration setup can be found here:
https://git.gsi.de/BEA_HDL/FPGA_Common#6-continuous-integration-environment

You can find instructions on how to program the FPGA and configure other hardware here:

https://git.gsi.de/BEA_HDL/FPGA_Common#7-programming-and-hardware-configuration

There are three different peripheral devices on each of the FMC ADC boards that have to be configured by the gateware. Since they have no persistent storage they have to configured after every power cycle:

• Si571 programmable VCXO
• AD9510 PLL and clock distribution
• ISLA216P ADC

The Si571 programmable VCXO is connected via I2C using 0x49 as device address. Additionally, there is an OE (output enable) pin, which has to be driven high or left unconnected since it provides an internal pullup. The device supports a maximum I2C bus speed of 400 kbit/s.

The startup frequency before configuration via I2C is 155.52 MHz. The Si571 is located below the heat spreader of the FMC board, which has to be unscrewed to read the labeling:

SiLabs 571
AJC000337 G
D09JW702+

The part properties can be decoded by providing the part number 571AJC000337 on a SiLabs web page [6]:

Product: Si571
Description: Differential/single-ended I2C programmable VCXO; 10-1417 MHz
Frequency A: 155.52 MHz
I2C Address (Hex Format): 49
Format: LVPECL
Supply Voltage: 3.3 V
OE Polarity: OE active high
Temperature Stability: 20 ppm
Tuning Slope: 135 ppm/V
Minimum APR: +/- 130 ppm
Frequency Range. 10 - 280 MHz
Operating Temp Range (C): -40 to +85

A datasheet can be found on the SiLabs website [7].

There are three adjustable parameters that define the output frequency:

where

• is the fixed internal quartz frequency of 114.285 MHz +/- 2000 ppm.
• has to be in the range .
• allowed values for are 4, 5, 6, 7, 9, 11
• allowed values for are 1 and all even numbers in

The three parameters should be chosen in a way that is minimal to reduce power consumption. If there should still be multiple possibilities for the choice of , one should choose as maximal.

For a desired output frequency of 125 MHz the optimum values are:

• = 5
• = 8
• = 43.750273439

Since the uncorrected frequency has an inaccuracy of 2000 ppm, one should read the initial value first and calculate

in order to get a more accurate result. is factory calibrated to compensate the actual frequency offset of .

The VCXO has a built-in configuration timeout of 10 ms. All I2C write operations from freezing to unfreezing the digitally controlled oscillator have to complete during this period to become active.

The following registers are read by the gateware for calculating the frequency correction:

Table 4.1: Si571 registers read by the gateware

The value of register 0x07 is only used to determine if the frequency has been programmed before, e.g. after a reloading of the bitstream of the FPGA without a power cycle of the FMC ADC board. The initial value of HSDIV is 4 and it is programmed to 5. Applying the frequency correction again would lead to a wrong result, since the RFREQ registers do not contain the factory defaults any more.

The following registers are programmed by the gateware after the calculation of the frequency correction:

Table 4.2: Si571 registers programmed by the gateware

The frequency was measured relatively to the processing clock of the AFC board.

The Analog Devices AD9510 is connected via SPI. Writing to registers must be completed with a write to the register address 0x5A with the LSBit set in the write value (e.g. 0x01) to take effect. Multiple writes can precede the writing of register 0x5A, so that this needs to be done only once at the end of a write sequence. The maximum SPI clock frequency is 25 MHz.

The phase frequency detector of the PLL, which compares the VCXO frequency to the reference frequency, has a maximum input frequency of 100 MHz. Higher frequencies have to be divided by the prescalers R (reference input) and N (VCXO input). A lock signal can be connected to a status pin, that is connected to a FPGA GPIO.

A datasheet can be found on the Analog Devices website [8].

The gateware configures the AD9510 device to lock the VCXO frequency to a reference clock coming from the FPGA.
The following registers are programmed by the gateware:

Table 4.3: AD9510 registers programmed by the gateware

The four ISLA216P ADCs are connected via SPI. The communication to each chip is enabled via an individual chip select line. The MOSI, MISO and CLK lines are shared between the four chips. Parallel configuration by driving all chip selects high at the same time works for the writing registers, but not for reading, since there would be multiple drivers on the MISO line. The maximum SPI clock frequency is given by the ADC sampling frequency divided by 16. At a sample frequency of 125 MHz this corresponds to a SPI clock frequency of 7.8125 MHz.

A datasheet can be found on the Renesas website [9].

The ADCs provide a configurable gain correction of +/- 4.2% and a configurable offset correction of +/- 138 LSBs. Since the gain correction and the offset correction are implemented digitally in the gateware, most of the configuration registers can be left at their default values.

The SPI interface in the gateware is implemented as a four wire interface, whereas the default setting of the ISLA216P SPI interface is a three wire mode. For being able to configure the ISLA216Ps interactively, the gateware configures the corresponding register to four wire mode at start up.

The following registers are programmed by the gateware:

Table 4.4: ISLA216P registers programmed by the gateware

The gateware uses three primary clocks:

• PCIe reference clock, 100 MHz
• FMC 0 ADC clock, 125 MHz
• FMC 1 ADC clock, 125 MHz

The PCIe reference clock comes from an output of an ADN4604 clock switch on the AFC board [11]. The clock switch is controlled via I2C by the MMC firmware to output a 100 MHz clock, which enters the FPGA as a differential input signal on pins H20 and G20. The PCIe reference clock feeds the reference clock input of the PCIe IP core by Xilinx, which contains a PLL producing a 125 MHz output clock for the AXI interface named clk_125_pcie_axi.

clk_125_pcie_axi drives a MMCM to generate:

• clk_125, 125 MHz, this is the main processing clock of the design
• clk_100, 100 MHz, used for reading the FPGA serial number
• clk_200, 200 MHz, used for the SDRAM interface IP core by Xilinx

The SDRAM interface IP core contains a MMCM which generates a 100 MHz clock named clk_100_sdram for the AXI interface.

On each of the two FMC boards there is a Si571 programmable VCXO (see chapter 4.1) which feeds the four ADCs. The frequency of the VCXO can be coupled to a reference clock coming from the FPGA (see chapter 4.2). The VCXO is programmed to a nominal output frequency of 125 MHz and coupled by the PLL with clk_125 coming from the FPGA. Bringing the PLL to lock is quite demanding, so that with the current settings a stable lock can not be guaranteed.

From each of the four ADCs of an FMC board an individual clock signal is led to the FPGA which is used for the deserialization in the IDDR primitives. For the further processing, only the clock signal from the first ADC of a FMC board is used since the clock frequencies of the four ADCs are identical.

There are two clock domain crossing FIFOs in the gateware to synchronize the data from the ADCs to the main processing clock clk_125.

As long as the PLL in the MMCM producing the main processing clock clk_125 is not yet in lock, the design is held in reset. After this the lock should be stable until the next power cycle.

The design will be reset whenever the PCIe connection is re-initialized. This happens e.g. when the FEC is rebooted.

There is a push button labeled RST at the center of the AFC front panel which is connected to the microcontroller for the MMC firmware. The OpenMMC firmware forwards a button press with a duration of at least two seconds to the FPGA pin AG26 as an active low signal to initiate a reset of the gateware.

Resetting the FPGA leads to the loss of the PCIe connection. To re-enable the connection, the FEC has to be rebooted.

Figure 5.1: Simplified data flow diagram

Figure 5.1 shows a simplified data flow diagram. For simplicity, some features are not included in the diagram:

• processing clocks and clock domain crossings
• resets
• gate and RF pulse inputs
• ADC data offset and gain corrections
• LEDs
• read out logics of FPGA serial number and build time stamp
• ADC maximum amplitude calculation
• signals connected to the observer
• data width conversions of AXI and AXI Stream connections

The data inputs from the ADCs require a latency correction to compensate clock and routing delays. This is implemented via individually configurable input delay primitives for both the clock and for the data input pins. By increasing the input delay of either a clock or of the associated data inputs, the alignment can be corrected in both directions.

The input delays provide a 32 tap delay line with a configurable delay between 0 to 31 taps [10]. Each tap corresponds to a delay of:

with being the frequency of the clock connected to the IDELAYCTRL primitive. With the 200 MHz clock connected in this design this corresponds to a tap delay value of 78 s.

The ADCs offers programmable user patterns that can be sent in place of the ADC samples to check the correct timing of the digital interface. For finding the optimum delay values, the following procedure is applied:

• The clock input delay is increased until the pattern begins to deteriorate and the delay index at which that happens is noted.
• After that the clock input delay is reset to 0 and the data delay is increased until the pattern begins to deteriorate.
• The optimum value is assumed to be the midpoint between these values.

For an ADC clock frequency of 125 MHz the optimal delay values are:

• FMC0: no deterioration at any clock delay, but deterioration at and above data delay 0x06
  • ADC clock delay value: 0x0D
  • ADC data delay value: 0x00
• FMC1: no deterioration at any clock delay, but deterioration at and above data delay 0x05
  • ADC clock delay value: 0x0D
  • ADC data delay value: 0x00

These values are programmed to the IDELAY primitives at start up. They can be changed via individual configuration registers (see chapter 7.1.2).

Even though the FMC clocks are coupled to the main processing clock by the FMC’s PLLs, they can jitter against the main processing clock or even run at a slightly different frequency if the PLLs unlock for any reason.

To prevent data corruption, two clock domain crossing FIFOs are used for the incoming ADC data, one for each FMC board. In the case of frequency deviations, there are two cases to differentiate:

• the FMC clock is running slightly faster than the processing clock:
  • one sample at a time will be discarded
  • this happens synchronous for all four ADCs of a FMC board
• the FMC clock is running slightly slower than the processing clock:
  • one sample at a time will be repeated
  • this happens synchronous for all four ADCs of a FMC board

Due to the synchronous handling of the four ADCs on a FMC board, the discarding or repetition of samples should not have any measurable effect on the BPM results, since the two inputs to each BPM come from the same FMC board.

The gate signal is fed to the FPGA via one of the eight MLVDS lines on the AMC connector. The selection is made via a configuration register (see chapter 6.2.2). The register’s default is to route MLVDS line 0 to the gate input of the BPM algorithm.

The pulses of the RF signal define the length of the linear regression in the BPM algorithm. The selection is made via a configuration register (see chapter 6.2.2). As a default, the RF signal is fed to the FPGA via the MMCX connector labeled TRIG on the front panel of FMC 1. In this case this signal is valid for both FMCs and the TRIG input of FMC 2 is not used.

The proportionality factor in equation 2.10 is set implicitly to 1 so that the result has to interpreted as a relative position in the range :

Equation 5.1: Normalized BPM algorithm

The capacitance correction (see chapter 2.1) and the linear regression (equation 4.1) are implemented as a pipelined algorithm. The processing clock is equal to the sampling frequency of the ADCs.

The gain correction, the differences and sums of the incoming ADC data pairs and and the four different sums of equation 4.1 are calculated every clock cycle.

• offset and gain corrected ADC 0 data sample is strobed unchanged. Input: 17 bits signed, output 17 bits signed
• offset and gain corrected ADC 1 data sample is multiplied with a correction factor coming from a configuration register. Input: 17 bits signed for data, 16 bits unsigned for correction factor, output 17 bits signed

• : sum of data 0 and data 1, inputs: 17 bits signed, output: 18 bits signed
• : difference of data 0 and data 1, inputs: 17 bits signed, output: 18 bits signed

The maximum word length of the adders in the DSP48 blocks of the FPGA is 48 bits. When using these adders, the maximum summation length is limited by the word length of longest term (36) to a value of 12.

• : inputs: 18 bits signed, output: 48 bits signed
• : input: 18 bits signed, output: 48 bits signed
• : input: 18 bits signed, output: 30 bits signed
• : input: 18 bits signed, output: 30 bits signed
• : counter, output: 12 bits unsigned

The following pipeline steps are only performed once for every linear regression period. The length of the linear regression period is defined by the BPM linear regression length register (see chapter 6.2.2).

If a RF signal is present, the length is additionally controlled by the distances of the pulses of this signal. A new linear regression calculation will be started with every rising edge of the RF signal, while the post processing steps for the previous period will be started.

The DSP48 blocks in the FPGA can only handle multiplications up to 18 bits times 25 bits. For this reason, a conversion to a floating point format is performed.

The floating point format is:

• : 18 bits signed (integer, not fractional as usual for floating point formats)
• : 6 bits unsigned

which decodes to:

The sums , , and are converted to float.

A conversion is not necessary for since it is only 12 bits wide.

The products , , and are calculated by multiplying the mantissas and by adding the exponents of the floating point representations.

In general the results of step 4 will have different exponents, so that the mantissas have to be shifted to a common exponent before a subtraction can take place.

The mantissa of the float number with the smaller exponent is shifted by the difference of exponents digits to the right and the exponent is set to the larger exponent. Sign extensions by 1 bit take place to prevent over- and underflows by the subtraction.

Now that the operands have the same exponent, the subtractions can take place by subtracting the mantissas.

The exponents of the results stay the same as that of the operands.

The results are: and

Due to the multiplication in step 4 and the sign extension in step 5 the mantissas have now a length of 37 bits, which is again too long for the final division. The mantissa is converted to the same floating point format as described in step 4.

The results respectively have a mantissa of 18 bits and two exponents of 6 bits each which have to be united in the next step.

Division is a costly operation in FPGAs. In this implementation it is performed by an IP core by Xilinx which is parametrized to 18 bits for both the divisor and the dividend. The result is 33 bits wide, of which 15 bits are fractional.

The division takes 25 clock cycles to complete. The divider IP core reaches a throughput of 1 in 3 clock cycles. Thus 3 is the lower limit for the linear regression length for the current settings of the IP core.

The exponents generated in step 7 are united to the existing ones from step 6 by addition.

The results of step 8 are pipelined until the completion of the division.

The division result is shifted to the right by minus the exponent from step 8. After that, the lower 16 bits are sliced to form the result of the linear regression algorithm.

The result has to be interpreted as a relative position in the range , multiplied by .

Two signals are created for debugging purposes and are connected to the observer (see https://git.gsi.de/BEA_HDL/FPGA_Common#23-observer):

• result out of range (1 bit): High if the absolute value of the numerator is greater than that of the denominator. This can happen if the phases of the two input signals are not aligned. In this case the result is set to the maximum or minimum value.
• division by zero (1 bit): Comes from the divider IP core and is high if the divisor is zero. This is very unlikely to happen. In this case the result is set to 0.

Allowed values for the linear regression length are: 3, 4, 5, … , 4096

The lower limit is caused by the divider IP core which can only handle one division in three clock cycles.

The upper limit is caused by the maximum operand length of the adder in the DSP48 primitives in the FPGA. A higher limit would be implementable at the cost of an increased resource usage and two additional clock cycles of processing latency.

The result from the BPM algorithm is sign extended and added up until the desired number of samples is reached. Only powers of two are allowed for the averaging length. Allowing any desired number would require a general division operation at the end of the averaging process, whereas a division by a power of two can be implemented by a simple shift operation. This is why the configuration register ’log2 of BPM averaging length’ contains the dual logarithm of the averaging length (see chapter 6.2.2).

The result is sliced to the same number of bits as the result from the BPM algorithm. It also has to be interpreted as a relative position in the range , multiplied by .

Available values for the averaging length are 1, 2, 4, … , 1,048,576.

The upper limit is not caused by any implementation limitation, but was simply chosen because longer averaging lengths were not assumed to be useful.

The memory mapped data transfers inside the FPGA are handled via the AXI protocol using a star topology with a central interconnect. The common data width is 256 bits and the common clock is the main processing clock of 125 MHz.

The AXI masters connected to the interconnect are:

• PCIe interface
• scope 0
• scope 1
• scope 2

The PCIe interface only supports an AXI data width of 128 bits, so that an AXI data width converter is used to be able to connect it to the interconnect. A clock domain crossing also takes place despite identical frequencies, since the AXI clock of the PCIe interface is derived directly from the PCIe reference clock and could jitter against the independently derived main processing clock.

The AXI slaves connected to the interconnect are:

• SDRAM interface
• register bank / Block RAM

The SDRAM interface only supports an AXI clock frequency of 100 MHz, so that an AXI clock converter is used to synchronize it to the main processing clock.

The AXI interconnect is configured to connect the scopes only to the SDRAM interface and only with write access since other accesses are not needed.

Even though there is no need for the PCIe interface to write to the SDRAM, this access is enabled because otherwise the PCIe driver will crash in case of an erroneous write access to the SDRAM.

The scopes internally use an AXI Stream bus to process the incoming data. The final data stream is converted to the AXI protocol.

There are three so called scopes for interactively storing calculation results. For the storage format of the scope data see chapter 6.1.

Since the frequency of the incoming ADC data samples is identical to the AXI clock, the data samples are parallized twice to allow flow controlled data processing. This also converts the 128 bits wide ADC data stream (8 * 16 bits) to the common AXI data width of 256 bits.

An IP core called AXI data mover manages the write access to the SDRAM. The block size of the AXI bus accesses is set to 4 MiBytes to allow a low protocol overhead. A block size of 256 bits (width of a single data word) would slow down the transmission in a way that the necessary data rate to store all incoming ADC data samples would not be reached.

The data rate of the BPM results is slow enough so that they do not have to be parallized before the transmission.

For the same reason, the block size of the AXI bus accesses can be set to the width of a single data word which simplifies the transmission handling.

The data rate of the BPM averaging results is even slower than that of the BPM results, so that the same mechanism can be used.

The peripheral devices documented in chapter 4 are initially programmed by the gateware. During operation, they can be configured using the corresponding gateware registers (see chapter 7.1.2).

There is an individual SPI interface for each of the two FMC boards. It is implemented as a four wire interface and connects to the four ADCs and to the PLL on the FMC ADC boards. The choice of the communication partner is implemented via indivial chip select lines.

There is an individual I2C interface for each of the two FMC boards. It only connects to the VCXO. The VCXO’s transaction timeout has to be kept in mind when programming it interactively (see chapter 4.1.

This gateware uses the Xilinx IP core DMA/Bridge Subsystem for PCI Express with the following configuration:

• PCIe speed: 5 GTransfers/s
• AXI clock frequency: 125 MHz
• reference clock frequency: 100 MHz

The PCIe reference clock is routed to the FPGA via the MMC firmware and is configured to be driven by the 100 MHz FCLKA clock coming from the AMC connector.

For the communication with the SDRAM, an IP core by Xilinx is used. The clock frequency of the SDRAM interface’s AXI bus is 100 MHz, so that an AXI clock converter is used to connect it to the rest of the AXI infrastructure which is clocked at 125 MHz.

This project incorporates the observer interface from the FPGA_Common Git submodule (see https://git.gsi.de/BEA_HDL/FPGA_Common#13-observer).

The following signals are connected to the observer inputs:

The rest of the multiplexer inputs are connected to zero.

The communication between the gateware and the software takes place via a PCIe driver by Xilinx called XDMA. There is only one PCIe Bar in use in the gateware which maps the memory space to different physical memories on the AMC board.

The following mapping is applied:

Table 6.1: Memory mapping

The architecture information and the observer are documented here:
https://git.gsi.de/BEA_HDL/FPGA_Common#2-common-monitoring-and-control-features

Read and write accesses are mapped to virtual file accesses:

• /dev/xdma0_c2h_0 for read accesses
• /dev/xdma0_h2c_0 for write accesses

Example in C:

uint32_t address = 0x00000000;
int fd = open("/dev/xdma0_c2h_0", O_RDWR);
lseek(fd, address, SEEK_SET);
uint64_t value;
read(fd, &value, sizeof(uint64_t));

It is important to write the whole register width of 64 bits. If a register has less than 64 bits, the unused MSBs have to be written to any value. 32 bit write accesses will not have any effect.

Example in C:

uint64_t value = 42;
uint32_t address = 0x00000400;
int fd = open("/dev/xdma0_h2c_0", O_RDWR);
lseek(fd, address, SEEK_SET);
write(fd, &value, sizeof(uint64_t));

Example in C:

uint32_t address = 0x80000000;
int fd = open("/dev/xdma0_c2h_0", O_RDWR);
lseek(fd, address, SEEK_SET);
char data[1024];
read(fd, data, 1024);

This example reads 1024 bytes of data from scope 0 to an array. For bigger data blocks, instead of using an array, you will probably prefer a dynamically allocated memory region.

There are three scope memory regions of which the one for the corrected ADC data is the largest since it has the highest data rate.

Table 6.2: Scopes memory map

The corrected ADC data is stored in the following format:

Table 6.3: Corrected ADC data storage format

The corrected data is the result of four sequential operations on the raw ADC data:

• offset correction by adding a correction summand
• gain correction by multiplying a correction factor
• configurable moving average filtering
• optional high pass filtering

The correction summand, the correction factor and the filter settings can be set by individual configuration registers (see chapter 6.2.2).

The corrected ADC data scope memory can hold up to samples. At a sampling frequency of 125 MHz this corresponds to a maximum capture duration of 0.537 seconds.

The BPM result is stored in the following format:

Table 6.4: BPM result storage format

The BPM result scope memory can hold up to samples. At a sampling frequency of 125 MHz and with a linear regression length of e.g. 1024 this corresponds to a maximum capture duration of 2:17 minutes.

This value divided by represents the relative beam position in the range .

This value divided by represents the variance of the corresponding BPM result multiplied with the linear regression length.

The scaling with the linear regression length guarantees enough LSBs to evaluate. The variance itself quantized with 16 bits would otherwise often result in zero.

The intensity of the beam. A value of corresponds to the maximum achievable intensity at an alternating pattern of maximum and minimum ADC samples on both inputs.

The BPM averaging result is stored in the following format:

Table 6.5: BPM averaging result storage format

The BPM averaging result scope memory can hold up to samples. At a sampling frequency of 125 MHz, with a linear regression length of e.g. 1024 and with an averaging length of e.g. 1024 this corresponds to a maximum capture duration of 39.1 hours.

This value divided by represents the relative beam position in the range .

This value divided by represents the variance of the corresponding BPM averaging result multiplied with the average linear regression length and the averaging length.

The scaling with the average linear regression length times the averaging length guarantees enough LSBs to evaluate. The variance itself quantized with 16 bits would otherwise nearly always result in zero.

The average intensity of the beam. A value of corresponds to the maximum achievable intensity at an alternating pattern of maximum and minimum ADC samples on both inputs.

The following status registers can be read by software:

Table 6.6: List of status registers

This value divided by represents the relative beam position in the range .

This value divided by represents the variance of the corresponding BPM result multiplied with the linear regression length.

The scaling with the linear regression length guarantees enough LSBs to evaluate. The variance itself quantized with 16 bits would otherwise often result in zero.

The intensity of the beam. A value of corresponds to the maximum achievable intensity at an alternating pattern of maximum and minimum ADC samples on both inputs.

The effective linear regression length is determined by the nominal value of the linear regression length configuration register and the frequency of the RF pulses. If no RF pulses are present, this register should hold the value of the linear regression length configuration register.

Counter value, driven by the 125 MHz main processing clock, starting from the high transition of the gate input signal.

This value divided by represents the relative beam position in the range . Due to the averaging there should be less noise on this value than on the BPM result.

This value divided by represents the variance of the corresponding BPM averaging result multiplied with the average linear regression length and the averaging length.

The scaling with the average linear regression length times the averaging length guarantees enough LSBs to evaluate. The variance itself quantized with 16 bits would otherwise nearly always result in zero.

The intensity of the beam. A value of corresponds to the maximum achievable intensity at an alternating pattern of maximum and minimum ADC samples on both inputs.

The average of the effective linear regression lengths of the BPM.

The value 0 is only present before starting the trigger for the first time. After that, the effective idle state is 3.

Address where the next data sample will be stored during the scope’s capturing process.

Time when the bitstream was created. This information can be used to identify the gateware version (together with the Git commit information documented in https://git.gsi.de/BEA_HDL/FPGA_Common#122-gateware-information).

Format:

The XDMA PCIe driver by Xilinx numbers the devices randomly and is not able to identify the slot number of an AMC board. This register holds the FPGA’s unique serial number and can be used to identify an AMC board.

The module ID can be used to identify the type of the current bitstream.
The module ID of the Cryring BPM gateware is 0x0102010300010001.

The fields are defined as follows:

Here is an incomplete list of project IDs:

The magic number can be used to determine if the gateware uses the expected register format.
The value of this register is the same for all module IDs: 0xBADEAFFEDEADC0DE.

The following registers can be written by software:

Table 6.7: List of configuration registers

Correction summand for a possible offset deviation of the ADC. The offset correction precedes the gain correction.

Correction factor for a possible gain deviation of the ADC. The default value 0x8000 corresponds to a multiplication by 1. The possible correction range is .

The capacitances of the two corresponding capacitor plates of a single BPM can differ. Data 0 is fed unchanged into the BPM algorithm, while data 1 is multiplied by a correction factor. The default value 0x8000 corresponds to a multiplication by 1. The possible correction range is .

Number of samples over which the linear regression is calculated if no external RF pulse signal is present. This value is valid for all four BPMs. If an external RF pulse signal is present, the result of the linear regression will be output and a new calculation will be started on every rising edge of the RF pulse signal. For this to work, this register has to be set to a value that is longer than the interval between the RF pulses.

Allowed values: 0x002 - 0xFFF

The lower limit is determined by the throughput of the divider IP core of 1 in 3 clock cycles that is used for the final division of the BPM algorithm.

Dual logarithm of the number of linear regression results over which the averaging is calculated. This value is valid for all four BPMs.

Allowed range: 0 .. 20. Higher values will be set to the maximum allowed value. This corresponds to an averaging length of 1, 2, 4, … , 1,048,576.

The gate signal input can be switched between one of the eight MLVDS lines on the backplane and the two MMCX connectors labeled TRIG on the FMC front panels.

The RF signal input can be switched between one of the eight MLVDS lines on the backplane and the two MMCX connectors labeled TRIG on the FMC front panels.

The intensity calculation in the BPM algorithm is normalized to ensure that no saturation can occur. This leads to small results during normal operation which are susceptible to quantization noise. By means of this register the normalization can be changed to allow larger results.

With each increment of this exponent by one, the result will double. Keep in mind that the result can saturate when setting this value to larger than zero.

The averaging length minus 1 of the moving average filter on the ADC data. All possible values from 0 to 1023 are allowed, resulting in an averaging length between 1 and 1024.

Bitmask which enables the IIR filter per BPM. The filter is intended to suppress a 70 kHz interference on certain BPMs. Bit 0 enables the filter on the data of ADC 0 and 1, bit 1 on the data of ADC 2 and 3 and so on.

The number of samples minus one that are stored after a scope has been triggered. Each sample consists of 16 bytes.

Scope 0 can only handle even numbers of samples. Uneven numbers will be automatically handled as the next higher even number. For scopes 1 and 2, also uneven numbers are allowed.

Writing a 1 to this register will arm the trigger once. The register does not have to be reset to 0 before the next arm trigger, just write another 1 to it. If the corresponding register continuous trigger is set to 1, writing to this register does not have any effect.

When in ’waiting for trigger’ state (see status register ’capture status’ in chapter 6.2.1), writing a 0 to this register will cancel the arming of the trigger and the capture status will change to ’done’.

A capture mode register is only available for scopes 1 and 2. Scope 0 (for corrected ADC data) always operates in capture mode 0.

Writing a 1 to this register triggers a reset on the gateware, which also resets all configuration registers to their default values.
The reset will be automatically lifted so that the register does not have to be written to 0 after initiating a reset.

A typical procedure for capturing a predefinable number of samples starting from the rising edge of the gate signal is the following:

• write the number of samples minus 1 to the configuration register capture length - 1
• write a 0 to the configuration register trigger mode
• write a 0 (= default) to the configuration register capture mode
• write a 1 to the configuration register arm trigger
• you can check the status register ’capture status’ for the progress: 1: rising edge of gate signal not yet detected, 2: capturing is ongoing, 3: capturing completed
• you can check the current write address by polling the status register next write address

BPM results are only calculated while the gate signal is high. If you want to capture a complete high period of e.g. BPM average samples, the total number of samples is unknown. Proceed as follows:

• write the maximum value 0x1FFFFFF to the configuration register capture length - 1
• write a 0 to the configuration register trigger mode
• write a 1 to the configuration register capture mode
• write a 1 to the configuration register arm trigger
• you can check the status register capture status as above
• the value of the status register next write address will be static after completion and indicates how many samples have been captured

Besides the interface documented in chapter 6 which is meant for productive use, there is an extended interface for development and debugging purposes. The extended interface is also present in the bitstream by default.

While the productive interface is intended to be kept as downward compatible as possible, the extended interface may be subject to major changes during the development process.

The following additional status registers can be read by software:

Table 7.1: List of additional status registers

Indicates that a SPI read or write access is going on. The value of this register has to be checked to be 0 before triggering a SPI access.

Contains the result of a read access to a SPI register.

Indicates that an I2C read or write access is going on. The value of this register has to be checked to be 0 before triggering an I2C access.

Contains the result of a read access to an I2C register.

Value of the configurable output pin status of the AD9510 PLL and clock distribution IC. By default this pin indicates lock status of the PLL.

RFREQ is a factory calibrated multiplicator to the XTAL frequency of the Si571 programmable VCXO. Before the programming of a new output frequency this value has to be read (see chapter 4.1).

The VCXO output frequency is programmed to 125 MHz by the gateware. This register holds the value of RFREQ that has been programmed (see chapter 4.1).

The ADC clock is measured against the main processing clock. This register holds the number of detected ADC clock cycles during 1 second of the main processing clock.

If the ADC clock is slower than the main processing clock, samples will be repeated by the clock domain crossing FIFO output logic. For each repetition the underflow counter will be incremented by 1.

If the ADC clock is faster than the main processing clock, samples will discarded by the clock domain crossing FIFO input logic. For each discarded sample the overflow counter will be incremented by 1.

The maximum and the minimum value of the ADC data is determined over a free running period of 1 second. This register contains the difference of the maximum and the minimum value.

The communication to the SDRAM is controlled by an IP core by Xilinx which performs a timing calibration at start up. The value of this register will be 1 after completion of the initial calibration.

The following additional registers can be written by software:

Table 7.2: List of additional configuration registers - part 1

Table 7.3: List of additional configuration registers - part 2

If set to 1, all eight ADC data inputs will be overridden by a counter value which is incremented by 1 every 125 MHz clock cycle.

If set to 1, the trigger is armed and will be rearmed automatically after every capture completion.

There is one tricolor LED at the center of the AFC front panel labeled L3 that can be controlled by the gateware.

value	input
0	PCIe reference clock, blink frequency divided by , white
1	static value from register 113 ’AFC LED value’

Static lighting pattern if register 112 ’AFC LED select’ = 1.

For testing purposes without an external gate signal this register can be set to 1 to simulate a gate signal via the register 115 ’gate override value’.

Can be used to simulate a gate signal when register 114 ’gate override’ is 1.

Determines the direction of the eight MLVDS lines on the AMC connector. A ’0’ corresponds to an input to the FPGA and a ’1’ to an output from the FPGA.

Determines the logic levels of the eight MLVDS lines if they are configured as outputs (see previous register).

There is one tricolor LED on the FMC front panel labeled status that can be controlled by the gateware.

value	input
0	ADC clock, blink frequency divided by , green if AD9510 PLL is in lock, otherwise red
1	AD9510 monitoring clock, blink frequency divided by
2, 3	static value from register ’status LED value’

The static lighting pattern defined by this register becomes active if the corresponding register ’status LED select’ is set to 2 or 3.

Chip select signals (active high) of the SPI bus to the four ADCs and to the AD9510 PLL and clock distribution.

0: write mode, 1: read mode

The address of the register that shall be accessed.

The data that shall be written to a register.

Write a 1 to this register to start a read or write access on the SPI bus. The register does not have to be reset to 0 before the next SPI trigger, just write another 1 to it.

Low active reset signal to the four ADCs in parallel. Tie to 0 and back to 1 to initiate a reset.

0: write mode, 1: read mode

The address of the connected VCXO is 0x49.

The address of the register that shall be accessed.

The data that shall be written to a register.

Write a 1 to this register to start a read or write access on the I2C bus. The register does not have to be reset to 0 before the next I2C trigger, just write another 1 to it.

Low active reset signal to the PLL and clock distribution. Tie to 0 and back to 1 to initiate a reset.

There is a separate clock switch in front of the AD9510 PLL reference clock input.

Enables the frequency output of the VCXO.

There is a configurable input delay for setting the correct digital interface timing for both the clock and the data signals. Increasing this value increases the delay of the clock, so that the data is sampled later.

See above. Increasing this value increases the delay of the data, so that the data is sampled at an earlier position.

There are three tricolor LEDs connected to FPGA pins:

• L3 in the center of the AFC front panel: Currently displays the PCIe reference clock divided by in white.
• LD1 (v1.0) or STATUS (v1.2 and v2.3) on the right of the two FMC board’s front panels: Currently display the ADC clock frequencies divided by in green if the PLLs indicate a lock, otherwise red.

Each tricolor LED consists of three independent LEDs (red, green and blue).

The LD1 (v1.0) or STATUS (v1.2 and v2.3) LED on the right of the FMC board front panel is connected differently between v1.0 and (v1.2 and v2.3). When using the location constraints for v1.2 and v2.3 together with a v1.0 board, the LED lights as follows:

• wanted red: off
• wanted green: lights green
• wanted blue: lights red

Also, the MMCX input TRIG seems to be connected differently on v1.0. Feeding HF-Pulses into v1.0 boards does not work with the current bitstream.

The FMC ADC boards were originally designed for very high input frequencies and are equipped with input filters that show a pronounced high pass characteristic. There are different versions of the boards which have a different ADC input filter circuitry.

Figure 8.1: Schematics of the original ADC input filter of versions 1.0 and 1.2. Image taken from [12]

Figure 8.2: Schematics of the original ADC input filter of version 2.3. Image taken from [13]

The part labeled TR1(B) BD0205F5050A00 is a balun with an operating range of 70 - 1000 MHz [14]. Lower frequencies are severely attenuated.

For being able to use the FMC ADC boards in the Cryring BPM system, the baluns have to be replaced by more suitable components.

Two approaches have been implemented on versions 1.0 and 1.2 (probably by Piotr Miedzik):

• each balun is replaced by two wires
• each balun is replaced by two capacitors of probably 100 nF (hint in an old email)

Figure 8.3: v1.2 ADC input filter: balun TR1B replaced by two capacitors

Figure 8.4: v1.0 ADC input filter: balun TR1B replaced by two wires

Figure 8.5: Original v2.3 ADC input filter

The heatspreader under the bottom of the FMC ADC board has to be unscrewed to access the baluns.

There is a significant difference in the ADC input filter circuitry between versions 1.0 and 1.2 and version 2.3. In version 2.3 the transmission line transformers L11 {A, B, C, D} have been removed and the RC filter has been modified.

Figure 8.6 shows the magnitude frequency responses of the original v2.3 input filter and of the two modifications of the v1.0 and v1.2 input filters. The diagram data was created by using a sine signal from a signal generator with an amplitude of 2 and by measuring the maximum amplitude swing of the raw ADC data.

Figure 8.6: Magnitude frequency responses of different ADC input filters

For being able to drive the reference clock of the PLLs on the FMC ADC boards from an FPGA output pin, a pullup resistor indicating the clock direction has to be desoldered. The resistor is labeled R132 in the FMC ADC schematic [13]. Figure 8.7 shows the location of the resistor.

Without this change slight clock frequency differences between the processing clock on the AFC board and the ADC clocks on the FMC boards occur. There are synchronization FIFOs which ensure correct clock domain crossings, but in this case a small fraction of ADC samples might have to be discarded or repeated once, depending on which frequency is higher. This will always affect all the samples of a FMC board in parallel, so that no differences between the two input data streams of a single BPM will occur and no measurable effect on the BPM results should be observed.

With this changes applied and with the correct settings of the PLL, the ADC samples of both FMC boards will arrive exactly in parallel and no samples will be lost or repeated.

Update: Even though removing the resistor is advisable, the PLL also locks with it in place. Not all the boards in the productive setup have been changed.

Figure 8.7: Pullup resistor which needs to be removed for the PLL to lock

The following AFC version 3.1 boards are installed in the productive setup in the Cryring container:

The FPGA serial number is not printed anywhere, but can only be read from the DNA_PORT primitive by the gateware. In this gateware the FPGA serial number is read out and stored in a register (see chapter 6.2.1).

The signal cables are connected as follows:

This test simulates the VHDL code of the gateware and is automatically run by the CI/CD pipelines of Gitlab.

All ADC data inputs are driven by the same repeated pattern of positive and negative values, but with different amplitudes.

For the same patterns on both inputs of a BPM with the amplitudes and ,

can be expressed as with

and equation 4.1 simplifies to:

Equation 9.1: equally_shaped_signal_bpm_result

so that the expected BPM result can be calculated as:

BPM	ADC	relative amplitudes ,	expected BPM result	simulated BPM result
0	0	1	10922.67	10922
	1	1/2
1	2	1/2	-10922.67	-10923
	3	1
2	4	1	0	0
	5	1
3	6	1	25486.22	25487
	7	1/8

The simulation results are consistent with the expectations considering possible numeric calculation deviations in the numerous calculation steps, which might influence the least significant bits.

The following measurement was made using a function generator which was configured to output two phase aligned sines with an amplitude of which were connected to the two inputs of a BPM.

The linear regression length and the averaging length were both set to 1024.

Before starting the measurement, the digital gain of one of the two ADC inputs was corrected so that the BPM averaging result equaled 0.

After that, the digital gain correction of the other ADC input was used to set different amplitudes in order to avoid possible nonlinearities of the function generator gain.

The results were read from the FPGA Observer GUI which displays the BPM results divided by .

relative amplitude	expected BPM result	measured BPM result
1/8	0.	0.778
2/8	0.6	0.600
3/8	0.	0.454
4/8	0.	0.333
5/8	0.2308	0.230
6/8	0.1429	0.142
7/8	0.0	0.066
8/8	0	0.000

The measurement results are consistent with the expectations considering noise and possible numeric calculation deviations in the numerous calculation steps, which might influence the least significant bits.

A test of the BPM scope and the BPM averaging scope was run overnight. The two inputs of a BPM were fed by two function generator outputs with the following settings:

• sine signal
• frequency: 1 MHz
• output to ADC0: 2.001
• output to ADC1: 0.667

According to equation 13.1, the expected BPM result for the chosen input amplitudes is 0.5.

The test was run for 12 hours, during which the scopes were read continuously and histograms of the occurring results were created.

Figure 9.1: BPM result histogram

The gateware was configured as follows:

• ADC1 gain correction: 0x8398 BPM averaging result = 0.5
• linear regression length: 1024
• averaging length: 1024
• number of samples per capture: 1024

Figure 9.2: BPM averaging result histogram

The resulting histograms do not show Gaussian distributions, but still seem to be reasonably confined. The deviations from Gaussian distributions might have been caused by temperature shifts during the night which might have affected the amplitudes.

[1] A. Reiter, R. Singh: Comparison of beam position calculation methods for application in digital acquisition systems. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, February 2018, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Paper_BPM_Algorithm.pdf

[2] P. Miedzik, H. Bräuning, T. Hoffmann, A. Reiter, R. Singh: A MicroTCA based beam position monitoring system at CRYRING@ESR. 16th Int. Conf. on Accelerator and Large Experimental Control Systems, Barcelona, Spain, October 2017, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Paper_BPM_architecture.pdf

[3] A. Reiter, W. Kaufmann, R. Singh, P. Miedzik, T. Hoffmann, H. Bräuning: The CRYRING BPM cookbook, March 2015, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Cryring_BPM_System_Overview.pdf

[4] AMC FMC Carrier (AFC) Git repository, Open Hardware Repository, https://ohwr.org/project/afc/wikis/home

[5] Xilinx: 7 Series FPGAs Data Sheet: Overview, https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf

[6] Silicon Labs (now Skyworks): Timing part decoder web page, https://tools.skyworksinc.com/TimingUtility/timing-part-number-search-results.aspx

[7] Silicon Labs: Si571 datasheet, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/si570.pdf

[8] Analog Devices: AD9510 datasheet, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/AD9510.pdf

[9] Renesas: ISLA216P datasheet, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/isla216p.pdf

[10] Xilinx: Artix 7 datasheet: DC and AC Switching Characteristics, https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf

[11] AFC v3.1 schematics, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Schematics_AFC_v3.1.pdf

[12] FMC ADC 250M 16B 4ch v1.2 schematics, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Schematics_FMC_ADC_250M_16B_4ch_v1_2.pdf

[13] FMC ADC 250M 16B 4ch v2.3 schematics, https://github.com/lnls-dig/fmc250-hw/blob/master/circuit_board/ADC.SchDoc

[14] Anaren: Balun BD0205F5050A00 datasheet, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Balun_BD0205F5050A00_datasheet.pdf