This documentation is automatically generated from the LaTeX sources by the script doc/tex/convert_tex_to_md.py. Any changes should be applied to the LaTeX sources.

A PDF of this documentation can be generated in the CI/CD section, see chapter 6.2.1.

All of the code of this project, the helper scripts and also the source of this documentation are under version control in a Git repository whose upstream is: https://git.gsi.de/BEA_HDL/Cryring_BPM_HDL_Code_new. The relevant branch is master.

Additional datasheets and papers are included as a Git submodule of the main Git repository. The upstream of the submodule is: https://git.gsi.de/BEA_HDL/datasheets and the relevant branch is master.

Installation scripts to set up a Gitlab runner for continuous integration including all necessary software to build the gateware can be found in a Git repository whose upstream is: https://git.gsi.de/BEA_HDL/Gitlab_Runner_Setup_Centos_7. The relevant branch is master.

This document describes the gateware ( = FPGA firmware) implementation of the Beam Position Monitor (BPM) for the Cryring accelerator at GSI. The term Trajectory Measurement System (TMS) is also common for this system and is used as a synonym for BPM.
There had been a previous implementation by Piotr Miedzik, but since no documentation could be found besides a conference paper [2], it was decided to reimplement the gateware.
The BPM measures the horizontal and vertical beam positions at nine places of the accelerator ring, resulting in 18 location results.

At each of the 18 measurement spots two capacitor plates are used to detect the electrostatic induction of the passing by charged particle bunches.

<b>Figure 1.1:</b> Mechanical drawing of a single BPM. The two segments of the slotted tube are the capacitor plates. The box on the top is the amplifier. Image taken from [3]

The 36 voltages of the capacitor plates are amplified and led via coaxial cables to a single evaluation point where the analog to digital conversion and the digital processing takes place.

<b>Figure 1.2:</b> Cryring BPM system overview. This document only describes the implementation of the block labeled 125 MSa/s ADC DAQ System (36 ch.), excluding the software part. Image taken from [3]

The positions of the particle beam are calculated respectively from the voltage difference of two related capacitor plates using the algorithm described in chapter 2.

Each of the 36 voltages coming from the amplifiers at the capacitor plates is sampled by a Renesas ISLA216P ADC at a sampling rate of 125 MHz with a resolution of 16 bits. Respectively four of the ADCs are placed on a single FMC board. Respectively two (ore only one for the last one) of the FMC boards are mounted on an AFC carrier board which is equipped with a Xilinx Kintex XC7A200T FPGA for data processing.

<b>Figure 1.3:</b> An AFC carrier board with a mounted ADC FMC board. The FPGA is located under the blue heat spreader. Image taken from [4]

The whole system uses five AFC carrier boards which are mounted in a MicroTCA crate together with a timing receiver and a CPU unit for post processing. Each of the five FPGAs is responsible for the processing of up to eight ADC data streams. The communication between the CPU unit and the FPGAs takes place via PCI Express over the so called backplane of the MicroTCA crate.

<b>Figure 1.4:</b> MicroTCA crate with from left to right: power supply, MCH, CPU unit, timing receiver, 5 AFC boards with 9 mounted FMC ADC boards, second MCH

This document describes the gatewares of the FPGAs on the five AFC carrier boards. The gatewares are identical independent of the number of mounted FMC boards.

The beam position is calculated from the measurement of the voltages of two corresponding plates:

\delta = a + \frac{x}{\kappa}\sigma

with

\delta=U_R-U_L

and

\sigma=U_R+U_L

where $`\kappa`$ is a proportionality factor influenced by the dimension of the measurement system, $`a`$ some possible voltage offset and $`x`$ the beam position.

The capacitance of the two corresponding capacitor plates can differ from their nominal value so that one of the voltages has to be corrected by multiplying a correction factor:

U_R=U_{R,orig}

U_L=c_L \cdot U_{L,orig}

The default value of $`c_L`$ in the gateware is 1. It is configurable by the software via register accesses.

A linear least squares approach is used to reduce measurement errors. The choice of the algorithm is described in [1]. The optimal approach would be an orthogonal least squares algorithm. Since the relative error of the difference signal $`\delta`$ dominates that of the sum signal $`\sigma`$, it can be simplified to a vertical least squares algorithm:

E(x,a) = \sum_i(a + {\frac{x}{\kappa}\sigma_i - \delta_i})^2

Minimizing

E(x,a)

via partial differentiation

\frac{\partial E}{\partial x} = 0

and

\frac{\partial E}{\partial a} = 0

leads to

\frac{x}{\kappa} = \frac{N\sum_i\sigma_i\delta_i-(\sum_i\sigma_i)(\sum_i\delta_i)}{N\sum_i\sigma_i^2-(\sum_i\sigma_i)^2}

<b>Equation 2.1:</b> BPM algorithm

For further reducing the data rate and reducing the measurement noise, the result of the least squares algorithm is averaged over an adjustable number of samples $`N`$. This is implemented via a simple block averaging:

x_{avg} = \frac{1}{N}\sum_{t=0}^{N-1}x(t)

There are three different peripheral devices on each of the FMC ADC boards that have to be configured by the gateware. Since they have no persistent storage they have to configured after every power cycle:

• Si571 programmable VCXO
• AD9510 PLL and clock distribution
• ISLA216P ADC

The Si571 programmable VCXO is connected via I2C using 0x49 as device address. Additionally, there is an OE (output enable) pin, which has to be driven high or left unconnected since it provides an internal pullup.

The startup frequency before configuration via I2C is 155.52 MHz. The Si571 is located below the heat spreader of the FMC board, which has to be unscrewed to read the labeling:

SiLabs 571
AJC000337 G
D09JW702+

The part properties can be decoded by providing the part number 571AJC000337 on a SiLabs web page [5]:

Product: Si571
Description: Differential/single-ended I2C programmable VCXO; 10-1417 MHz
Frequency A: 155.52 MHz
I2C Address (Hex Format): 49
Format: LVPECL
Supply Voltage: 3.3 V
OE Polarity: OE active high
Temperature Stability: 20 ppm
Tuning Slope: 135 ppm/V
Minimum APR: +/- 130 ppm
Frequency Range. 10 - 280 MHz
Operating Temp Range (C): -40 to +85

A datasheet can be found on the SiLabs website [6].

There are three adjustable parameters that define the output frequency:

f_{out} = \frac{f_{XTAL} \cdot RFREQ}{HSDIV \cdot N1}

where

• $`f_{XTAL}`$ is the fixed internal quartz frequency of 114.285 MHz +/- 2000 ppm.
• $`f_{XTAL} \cdot RFREQ`$ has to be in the range $`[4850 \mathrm{MHz},5670 \mathrm{MHz}]`$.
• allowed values for $`HSDIV`$ are 4, 5, 6, 7, 9, 11
• allowed values for $`N1`$ are 1 and all even numbers in $`[2,128]`$

The three parameters should be chosen in a way that $`RFREQ`$ is minimal to reduce power consumption. If there should still be multiple possibilities for the choice of $`HSDIV \cdot N1`$, one should choose $`HSDIV`$ as maximal.

For a desired output frequency of 125 MHz the optimum values are:

• $`HSDIV`$ = 5
• $`N1`$ = 8
• $`RFREQ`$ = 43.750273439

Since the uncorrected $`f_{XTAL}`$ frequency has an inaccuracy of 2000 ppm, one should read the initial $`RFREQ`$ value first and calculate

RFREQ = RFREQ_{init} \cdot \frac{f_{out} \cdot HSDIV \cdot N1}{f_{out,init} \cdot HSDIV_{init} \cdot N1_{init}}

in order to get a more accurate result. $`RFREQ_{init}`$ is factory calibrated to compensate the actual frequency offset of $`f_{XTAL}`$.

The following registers are read by the gateware for calculating the frequency correction:

<b>Table 3.1:</b> Si571 registers read by the gateware

The value of register 0x07 is only used to determine if the frequency has been programmed before, e.g. after a reloading of the bitstream of the FPGA without a power cycle of the FMC ADC board. Applying the frequency correction again would lead to a wrong result, since the RFREQ registers do not contain the factory defaults any more.

The following registers are programmed by the gateware after the calculation of the frequency correction:

<b>Table 3.2:</b> Si571 registers programmed by the gateware

The Analog Devices AD9510 is connected via SPI. Writing to registers must be completed with a write to the register address 0x5A with the LSBit set in the write value (e.g. 0x01) to take effect. Multiple writes can precede the writing of register 0x5A, so that this needs to be done only once at the end of a write sequence. The maximum SPI clock frequency is 25 MHz.
The phase frequency detector of the PLL, which compares the VCXO frequency to the reference frequency, has a maximum input frequency of 100 MHz. Higher frequencies have to be divided by the prescalers R (reference input) and N (VCXO input). A lock signal can be connected to a status pin, that is connected to a FPGA GPIO.

A datasheet can be found on the Analog Devices website [7].

The gateware configures the AD9510 device to lock the VCXO frequency to a reference clock coming from the FPGA.
The following registers are programmed by the gateware:

<b>Table 3.3:</b> AD9510 registers programmed by the gateware

The four ISLA216P ADCs are connected via SPI. Each chip is enabled via an individual chip select line. The MOSI, MISO and CLK lines are shared between the four chips. Parallel configuration by driving all chip selects high at the same time works for the writing registers, but not for reading, since there would be multiple drivers on the MISO line. The maximum SPI clock frequency is given by the ADC sampling frequency divided by 16. At a sample frequency of 125 MHz this corresponds to a SPI clock frequency of 7.8125 MHz.

A datasheet can be found on the Renesas website [8].

The ADCs provide a configureable gain correction of +/- 4.2% and a configureable offset correction of +/- 138 LSBs. Since the gain correction and the offset correction are implemented digitally in the gateware, most of the configuration registers can be left at their default values.
The SPI interface in the gateware is implemented as a four wire interface, whereas the default setting of the ISLA216P SPI interface is a three wire mode. For being able to configure the ISLA216Ps interactively, the gateware configures the corresponding register to four wire mode at start up.

The following registers are programmed by the gateware:

<b>Table 3.4:</b> ISLA216P registers programmed by the gateware

The gateware uses three primary clocks:

• PCIe reference clock, 100 MHz
• FMC 0 ADC clock, 125 MHz
• FMC 1 ADC clock, 125 MHz

The PCIe reference clock comes from an output of an ADN4604 clock switch an the AFC board [9]. The clock switch is controlled via I2C by the MMC firmware to output a 100 MHz clock, which enters the FPGA as a differential input signal on pins H20 and G20. The PCIe reference clock feeds the reference clock input of the PCIe IP core by Xilinx, which contains a PLL producing a 125 MHz output clock for the AXI interface named clk_125_pcie_axi.

clk_125_pcie_axi drives a MMCM to generate:

• clk_125, 125 MHz, this is the main processing clock of the design
• clk_100, 100 MHz, used for reading the FPGA serial number
• clk_200, 200 MHz, used for the SDRAM interface IP core by Xilinx

The SDRAM interface IP core contains a MMCM which generates a 100 MHz clock named clk_100_sdram for the AXI interface.

On each of the two FMC boards there is a Si571 programmable VCXO (see chapter 3.1) which feeds the four ADCs. The frequency of the VCXO can be coupled to a reference clock coming from the FPGA (see chapter 3.2). The VCXO is programmed to a nominal output frequency of 125 MHz and coupled by the PLL with clk_125 coming from the FPGA. Bringing the PLL to lock is quite demanding, so that with the current settings a stable lock can not be guaranteed.

From each of the four ADCs of an FMC board an individual clock signal is led to the FPGA which is used for the deserialization in the IDDR primitives. For the further processing, only the clock signal from the first ADC of a FMC board is used since the clock frequencies of the four ADCs are identical.

There are two clock domain crossing FIFOs in the gateware to synchronize the data from the ADCs to the main processing clock clk_125.

The gateware uses two reset sources:

• main PLL not in lock
• reset button on the AFC front panel

As long as the PLL in the MMCM producing the main processing clock clk_125 is not yet in lock, the design is held in reset. After this the lock should be stable until the next power cycle.

There is a push button labeled RST at the center of the AFC front panel which is connected to the microcontroller for the MMC firmware. The firmware should forward a button press to the FPGA pin AG26 as an active low signal to initiate a reset of the gateware.
With the actual OpenMMC firmware this forwarding does not work, so that pressing the RST button does not have any effect.

The proportionality factor $`\kappa`$ in equation 2.1 is set implicitly to 1 so that the result has to interpreted as a relative position in the range $`[-1, 1]`$:

x = \frac{N\sum_i\sigma_i\delta_i-(\sum_i\sigma_i)(\sum_i\delta_i)}{N\sum_i\sigma_i^2-(\sum_i\sigma_i)^2}

<b>Equation 4.1:</b> Normalized BPM algorithm

The capacitance correction (see chapter 2.1) and the linear regression (equation 4.1) are implemented as a pipelined algorithm. The processing clock is equal to the sampling frequency of the ADCs.

The gain correction, the differences and sums of the incoming ADC data pairs $`\sigma`$ and $`\delta`$ and the four different sums of equation 4.1 are calculated every clock cycle.

• offset and gain corrected ADC 0 data sample is strobed unchanged. Input: 17 bits signed, output 17 bits signed
• offset and gain corrected ADC 1 data sample is multiplied with a correction factor coming from a configuration register. Input: 17s bit signed for data, 16 bits unsigned for correction factor, output 17 bits signed

• $`\sigma`$: sum of data 0 and data 1, inputs: 17 bits signed, output: 18 bits signed
• $`\delta`$: difference of data 0 and data 1, inputs: 17 bits signed, output: 18 bits signed

The maximum word length of the adders in the DSP48 blocks of the FPGA is 48 bits. When using these adders, the maximum summation length is limited by the word length of longest term $`\sigma\delta`$ (36) to a value of 12.

• $`\sum_i\sigma_i\delta_i`$: inputs: 18 bits signed, output: 48 bits signed
• $`\sum_i\sigma_i^2`$: input: 18 bits signed, output: 48 bits signed
• $`\sum_i\sigma_i`$: input: 18 bits signed, output: 30 bits signed
• $`\sum_i\delta_i`$: input: 18 bits signed, output: 30 bits signed
• $`N`$: counter, output: 12 bits unsigned

The following pipeline steps are only performed once for every linear regression period. The length of the linear regression period is defined by the BPM linear regression length register (see chapter 7.2.1).

If a RF signal is present, the length is additionally controlled by the distances of the pulses of this signal. A new linear regression calculation will be started with every rising edge of the RF signal, while the post processing steps for the previous period will be started.

The DSP48 blocks in the FPGA can only handle multiplications up to 18 bits times 25 bits. For this reason, a conversion to a floating point format is performed.

The floating point format is:

• $`mantissa`$: 18 bits signed (integer, not fractional as usual for floating point formats)
• $`exponent`$: 6 bits unsigned

which decodes to: $`value = mantissa \cdot 2^{exponent}`$

The sums $`\sum_i\sigma_i\delta_i`$, $`\sum_i\sigma_i^2`$, $`\sum_i\sigma_i`$ and $`\sum_i\delta_i`$ are converted to float.

A conversion is not necessary for $`N`$ since it is only 12 bits wide.

The products $`N\sum_i\sigma_i\delta_i`$, $`(\sum_i\sigma_i)(\sum_i\delta_i)`$, $`N\sum_i\sigma_i^2`$ and $`(\sum_i\sigma_i)^2`$ are calculated by multiplying the mantissas and by adding the exponents of the floating point representations.

In general the results of step 4 will have different exponents, so that the mantissas have to be shifted to a common exponent before a subtraction can take place.

The mantissa of the float number with the smaller exponent is shifted by the difference of exponents digits to the right and the exponent is set to the larger exponent. Sign extensions by 1 bit take place to prevent over- and underflows by the subtraction.

Now that the operands have the same exponent, the subtractions can take place by subtracting the mantissas.
The exponents of the results stay the same as that of the operands.

The results are: $`N\sum_i\sigma_i\delta_i-(\sum_i\sigma_i)(\sum_i\delta_i)`$ and $`N\sum_i\sigma_i^2-(\sum_i\sigma_i)^2`$

Due to the multiplication in step 4 and the sign extension in step 5 the mantissas have now a length of 37 bits, which is again too long for the final division. The mantissa is converted to the same floating point format as described in step 4.

The results respectively have a mantissa of 18 bits and two exponents of 6 bits each which have to be united in the next step.

Division is a costly operation in FPGAs. In this implementation it is performed by an IP core by Xilinx which is parametrized to 18 bits for both the divisor and the dividend. The result is 33 bits wide, of which 15 bits are fractional.

The division takes 25 clock cycles to complete. The divider IP core reaches a throughput of 1 in 3 clock cycles. Thus 3 is the lower limit for the linear regression length for the current settings of the IP core.
The exponents generated in step 7 are united to the existing ones from step 6 by addition.

The divider IP core only handles the mantissas. The exponents of the dividend and the divisor are subtracted.

The results of step 9 are pipelined until the completion of the division.

The division result is shifted to the right by minus the exponent from step 9. After that, the lower 16 bits are sliced to form the result of the linear regression algorithm.

The result has to be interpreted as a relative position in the range $`[-1,1[`$, multiplied by $`2^{15}`$.

Two signals are created for debugging purposes and are connected to the signal observer (see chapter 4.7.2):

• result out of range (1 bit): High if the absolute value of the numerator is greater than that of the denominator. This can happen if the phases of the two input signals are not aligned. In this case the result is set to the maximum or minimum value.
• division by zero (1 bit): Comes from the divider IP core and is high if the divisor is zero. This is very unlikely to happen. In this case the result is set to 0.

Allowed values for the linear regression length are: 3, 4, 5, … , 4096

The lower limit is caused by the divider IP core which can only handle one division in three clock cycles.

The upper limit is caused by the maximum operand length of the adder in the DSP48 primitives in the FPGA. A higher limit would be implementable at the cost of increased resource usage and two additional clock cycles of processing latency.

The result from the BPM algorithm is sign extended and added up until the desired number of samples is reached. Only powers of two are allowed for the averaging length. Allowing any desired number would require a general division operation at the end of the averaging process, whereas a division by a power of two can be implemented by a simple shift operation. This is why the configuration register ’log2 of BPM averaging length’ contains the dual logarithm of the averaging length (see chapter 7.2.1).
The result is sliced to the same number of bits as the result from the BPM algorithm. It also has to be interpreted as a relative position in the range $`[-1,1[`$, multiplied by $`2^{15}`$.

Available values for the averaging length are 1, 2, 4, … , 1,048,576.

The upper limit is not caused by any implementation limitation, but was simply chosen because longer averaging lengths were not assumed to be useful.

There is a continous integration environment setup for the Cryring_BPM_HDL_Code_new Git repository. It is implemented as a so called Gitlab Runner that communicates with the remote of the Git repository, the Gitlab server git.gsi.de.

At the moment the Gitlab Runner is running on the Linux server sdlx035 located in a server room in the basement.

The benefits of continuous integration are:

• every change will be tested automatically
• it is ensured that no files are missing in the repository
• the master branch can be kept functional at any time
• build results like e.g. bitstreams are automatically generated and can be archived

<b>Figure 6.1:</b> Gitlab: continuous integration pipelines

There is an installation script install.sh in the Gitlab_Runner_Setup_Centos_7 Git repository. It installs the Gitlab Runner as well as the software needed for simulation, generation of documentation and building an FPGA.

After the installation, the newly setup Gitlab Runner has to configured to connect to a remote repository on a Gitlab server. In the repository’s web front end on the Gitlab server, go to Settings CI/CD Runners and copy the registration token which you will need in the following step.

On the newly installed Gitlab Runner server, open a terminal and type sudo gitlab-runner register.
Enter the following information:

• gitlab-ci coordinator URL: e.g. https://git.gsi.de
• gitlab-ci token: enter the registration token copied before
• gitlab-ci description: name of the server, e.g. sdlx035
• gitlab-ci tags: leave empty
• executor: shell

You can add multiple repositories with different tokens by running sudo gitlab-runner register multiple times.

Each push to the Gitlab server will trigger a so called continuous integration / continuous delivery (CI/CD) pipeline. The pipeline setup is defined by the file gitlab-ci.yml in the root folder of the repository. The following pipeline stages are defined:

• documentation
• simulation
• FPGA build

<b>Figure 6.2:</b> Gitlab: Pipeline stages

The script create_documentation.sh in doc/tex is run to generate this documentation from the Latex source files. Pdflatex is run twice by the script to allow the generation of references inside the document. This pipeline stage succeeds if Pdflatex can generate the PDF without errors.

The log file of Pdflatex and - if successful - the PDF of the documentation are archived.

The script run/run_simulation.sh is run which uses the Vivado command line interface to simulate the top level of the gateware. Test signals from the ADCs are generated as inputs to the simulation. The BPM results are saved to a file which is compared to a reference pattern. This pipeline stage succeeds if there is no error in simulation and if the BPM result file matches the reference pattern.

The log file of the simulation and - if successful - a file with the BPM results from the simulaton are archived.

The script run/run_build_flow.sh is run which uses the Vivado command line interface to build the gateware. This pipeline stage succeeds if there is no error during the build process and if a bitstream file has been generated.

Different log files from synthesis and implementation, different reports like utilization and timing reports and - if successful - the bitstream file are archived.

<b>Figure 6.3:</b> Gitlab: Pipeline progress console

For each of the pipeline stages the archiving of build results can be configured for an adjustable time period, which is set to one week. If the period has passed and the build results have been deleted, they can be generated again by restarting the pipeline.

The build results can be downloaded from the Gitlab web frontend where they are called job artifacts (see figure 6.3).

$`\color{green}{\text{\textbf{The CI/CD pipelines can also be used to generate FPGA bitstreams without having to set up a build environment.}}}`$

The communication between the gateware inside the FPGA and the software running on the CPU unit takes place via a PCIe driver by Xilinx called XDMA.

There is only one PCIe Bar in use in the gateware which maps a coherent memory space of 0x80010000 bytes (= 2,147,549,184 in decimal) to different physical memories on the AFC board.

The following mapping is applied:

<b>Table 7.1:</b> Memory mapping

There are three scope memory regions of which the one for the corrected ADC data is the largest since it has the highest data rate.

<b>Table 7.2:</b> Scopes memory map

The corrected ADC data is stored in the following format:

<b>Table 7.3:</b> Corrected ADC data storage format

The corrected data is the result of two sequential operations on the raw ADC data:

1. offset correction by adding a correction summand
2. gain correction by multiplying a correction factor

The correction summand and the correction factor can be set by individual configuration registers (see chapter 7.2.1).

The corrected ADC data scope memory can hold up to $`2^{26}`$ samples. At a sampling frequency of 125 MHz this corresponds to a maximum capture duration of 0.537 seconds.

The BPM result is stored in the following format:

<b>Table 7.4:</b> BPM result storage format

The BPM result scope memory can hold up to $`2^{25}`$ samples. At a sampling frequency of 125 MHz and with a linear regression length of e.g. 1024 this corresponds to a maximum capture duration of 4:35 minutes.

The BPM averaging result is stored in the following format:

<b>Table 7.5:</b> BPM averaging result storage format

The BPM averaging result scope memory can hold up to $`2^{25}`$ samples. At a sampling frequency of 125 MHz, with a linear regression length of e.g. 1024 and with an averaging length of e.g. 1024 this corresponds to a maximum capture duration of 78.2 hours.

The following registers can be written by software:

<b>Table 7.6:</b> List of configuration registers

Correction summand for a possible offset deviation of the ADC. The offset correction precedes the gain correction.

Correction factor for a possible gain deviation of the ADC. The default value 0x8000 corresponds to a multiplication by 1. The possible correction range is $`[0, 2[`$.

The capacitances of the two corresponding capacitor plates of a single BPM can differ. Data 0 is fed unchanged into the BPM algorithm, while data 1 is multiplied by a correction factor. The default value 0x8000 corresponds to a multiplication by 1. The possible correction range is $`[0, 2[`$.

Number of samples over which the linear regression is calculated if no external RF pulse signal is present. This value is valid for all four BPMs. If an external RF pulse signal is present, the result of the linear regression will be output and a new calculation will be started on every rising edge of the RF pulse signal. For this to work, this register has to be set to a value that is longer than the interval between the RF pulses.

Allowed values: 0x0002 - 0xFFFF

The lower limit is determined by the throughput of the divider IP core of 1 in 3 clock cycles that is used for the final division of the BPM algorithm.

Dual logarithm of the number of linear regression results over which the averaging is calculated. This value is valid for all four BPMs. Allowed range: 0 .. 20. Higher values will be set to the maximum allowed value. This corresponds to an averaging length of 1, 2, 4, … , 1,048,576.

The gate signal input can be switched between one of the eight MLVDS lines on the backplane and the two MMCX connectors labeled TRIG on the FMC front panels.

The RF signal input can be switched between one of the eight MLVDS lines on the backplane and the two MMCX connectors labeled TRIG on the FMC front panels.

The number of samples minus one that are stored after a scope has been triggered. Each sample consists of 16 bytes.

If set to 1 the trigger is armed and will be rearmed automatically after every capture completion.

Writing a 1 to this register will arm the trigger once. The register does not have to be reset to 0 before the next arm trigger, just write another 1 to it. If the corresponding register ’continuous trigger’ is set to 1, writing to this register does not have any effect.

A capture mode register is only available for scopes 1 and 2. Scope 0 (for corrected ADC data) always operates in capture mode 0.

The following status registers can be read by software:

<b>Table 7.7:</b> List of status registers

This value divided by $`2^{15}`$ represents the relative beam position in the range $`[-1, 1[`$.

This value divided by $`2^{15}`$ represents the relative beam position in the range $`[-1, 1[`$. Due to the averaging there should be less noise on this value than on the BPM result.

The value 0 is only present before starting the trigger for the first time. After that, the effective idle state is 3.

Address where the latest data sample was stored during the scope’s capturing process.

The XDMA PCIe driver by Xilinx numbers the devices randomly and is not able to identify the slot number of an AFC board. This register holds the FPGA’s unique serial number and can be used to identify an AFC board.

A typical procedure for capturing a predefineable number of samples starting from the rising edge of the gate signal is the following:

• write the number of samples minus 1 to the configuration register ’capture length - 1’
• write a 1 to the configuration register named ’arm trigger’
• you can check the status register named ’capture status’ for the progress: 1: rising edge of gate signal not yet detected, 2: capturing is ongoing, 3: capturing completed
• you can check the current write address by polling the status register named ’latest write address’

BPM results are only calculated while the gate signal is high. If you want to capture a complete high period of e.g. BPM average samples, the total number of samples is unknown. Proceed as follows:

• write the maximum value 0x1FFFFFF to the configuration register named ’capture length - 1’
• write a 1 to the configuration register named ’capture mode’
• write a 1 to the configuration register named ’arm trigger’
• you can check the status register ’capture status’ as above
• the value of the status register named ’latest write address’ will be static after completion and indicates how many samples have been captured

Besides the interface documented in chapter 7 which is meant for productive use, there is an extended interface for development and debugging purposes. The extended interface is also present in the bitstream by default. While the productive interface is intended to be kept as downward compatible as possible, the extended interface may be subject to major changes during the development process.

The following additional registers can be written by software:

<b>Table 8.1:</b> List of additional configuration registers - part 1

<b>Table 8.2:</b> List of additional configuration registers - part 2

There is one tricolor LED on the FMC front panel labeled status that can be controlled by the gateware.

Static lighting pattern if register ’status LED select’ = 2 or 3.

Chip select signals (active high) of the SPI bus to the four ADCs and to the AD9510 PLL and clock distribution.

0: write mode, 1: read mode

The address of the register that shall be accessed.

The data that shall be written to a register.

Write a 1 to this register to start a read or write access on the SPI bus. The register does not have to be reset to 0 before the next SPI trigger, just write another 1 to it.

Low active reset signal to the four ADCs in parallel. Tie to 0 and back to 1 to initiate a reset.

0: write mode, 1: read mode

The address of the connected VCXO is 0x49.

The address of the register that shall be accessed.

The data that shall be written to a register.

Write a 1 to this register to start a read or write access on the I2C bus. The register does not have to be reset to 0 before the next I2C trigger, just write another 1 to it.

Low active reset signal to the PLL and clock distribution. Tie to 0 and back to 1 to initiate a reset.

There is a separate clock switch in front of the AD9510 PLL reference clock input.

Enables the frequency output of the VCXO.

There is a configurable input delay for setting the correct digital interface timing for both the clock and the data signals. Increasing this value increases the delay of the clock, so that the data is sampled later.

See above. Increasing this value increases the delay of the data, so that the data is sampled at an earlier position.

When productive mode is 1, scope 0 operates in an easy to use mode for storing ADC data.
Setting this register to 0 enables additional functionality like combining and choosing different signals to store and a more powerful and flexible two-stage trigger.
Registers 117 to 127 are only relevant in non productive mode.

There is one tricolor LED at the center of the AFC front panel labeled L3 that can be controlled by the gateware.

Static lighting pattern if register 113 ’AFC LED select’ = 1.

For testing purposes without an external gate signal you can set this register to 1 and simulate a gate signal via register 116 ’gate override value’.

Can be used to simulate a gate signal when register 115 ’gate override’ is 1.

Determines the data valid input to the observer. Samples are only stored when the valid signal is high.

The observer stores samples that are 128 bits wide, which consist of two concatenated 64 bits wide multiplexer outputs. Each multiplexer can choose between eight different input vectors. Like this, each signal can be observed in parallel to any other signal.

For a detailed description of the input vectors see chapter 4.7.2.

The number of samples minus one that are stored after the observer has been triggered. Each sample consists of 16 bytes.

Analog to register 120 and 121. Determines on which observer input vector the trigger listens.

64 bit wide compare vector that is compared with the observer input vector determined by register 123 ’observer trigger select’. If the two pattern match, the next sample will be compared to the compare vector determined by register 125: ’trigger compare vector (t = 0)’.

See above. If the patterns do not match, the next sample will be compared to the compare vector determined by register 124: ’trigger compare vector (t = -1)’. If the patterns match the data acquisition is triggered.

Determines which bits of the input vector shall be compared with that of the compare vectors. Valid for both trigger compare vectors (registers 124 and 125). For a triggering, the patterns must match for all bits where the bit mask is 1.

Starts the comparing process. Data is captured if the patterns defined by the previous three registers match.

The following additional status registers can be read by software:

<b>Table 8.3:</b> List of additional status registers

Indicates that a SPI read or write access is going on. The value of this register has to be checked to be 0 before triggering a SPI access.

Contains the result of a read access to a SPI register.

Indicates that an I2C read or write access is going on. The value of this register has to be checked to be 0 before triggering an I2C access.

Contains the result of a read access to an I2C register.

Value of the configurable output pin status of the AD9510 PLL and clock distribution IC. By default this pin indicates lock status of the PLL.

RFREQ is a factory calibrated multiplicator to the XTAL frequency of the Si571 programmable VCXO. Before the programming of a new output frequency this value has to be read (see chapter 3.1).

The VCXO output frequency is programmed to 125 MHz by the gateware. This register holds the value of RFREQ that has been programmed (see chapter 3.1).

The ADC clock is measured against the main processing clock. This register holds the number of detected ADC clock cycles during 1 second of the main processing clock.

If the ADC clock is slower than the main processing clock, samples will be repeated by the clock domain crossing FIFO output logic. For each repetition the underflow counter will be incremented by 1.

If the ADC clock is faster than the main processing clock, samples will discarded by the clock domain crossing FIFO input logic. For each discarded sample the overflow counter will be incremented by 1.

The maximum and the minimum value of the ADC data is determined over a free running period of 1 second. This register contains the difference of the maximum and the minimum value.

The communication to the SDRAM is controlled by an IP core by Xilinx which performs a timing calibration at start up. The value of this register will be 1 after completion of the initial calibration.

Indicates that the observer has been triggered.

Indicates that a capturing process is ongoing.

Time when the bitstream was created. Can be used to identify the gateware version (together with the Git commit information documented in chapter 8.2.3). Format:

The first seven eights of the Block RAM (see memory mapping, table 7.1) are used to store information about the observer signals, the registers and the gateware version.

Information about the signals connected to the eight observer multiplexer inputs is stored in the first half of the Block RAM. Following information is stored for every bit of each of the eight 64 bits wide multiplexer inputs:

name of signal (30 bytes), display type of signal (1 byte), bit index in signal (1 byte)

<b>Table 8.4:</b> Observer signal information storage format

Table 8.4 shows the storage format of the 512 entries, each of which has a width of 32 bytes. The coding of the display type byte is the following:

The names are stored as ASCII strings. If a name is shorter than 30 bytes, the remaining bytes are filled with Null characters.
The observer signal information is used by the FPGA Observer software to display the observer signals in the Data Acquisition tab (see chapter 9.1.3). The information is also used to format the measurement data to be displayed by GTKWave.

Information about the 128 configuration registers and the 128 status registers is stored in the third quarter of the Block RAM. Following information is stored for every register:

name of register (31 bytes), number of bits (1 byte)

<b>Table 8.5:</b> Register information storage format

Table 8.5 shows the storage format of the 256 entries, each of which has a width of 32 bytes. The names are stored as ASCII strings. If a name is shorter than 31 bytes, the remaining bytes are filled with Null characters. If not all registers are in use, a width of 0 bits indicates that a register is not present.
The register information is used by the FPGA Observer software to display the registers in the Register Access tab (see chapter 9.1.2).

The address range from 0x80006000 to 0x80006FFF is used to store information about the gateware version. The information is stored as an ASCII string of variable length (maximum 4 kiB), which is assembled from information from the Git repository. It contains the URL of the remote server of the Git repository, the latest commit hash and the latest commit date.
The gateware information is used by the FPGA Observer software to display the information in the Gateware Information tab (see chapter 9.1.6), except from the bitstream generation date, which is read from status register 126 ’build timestamp’.

There is a graphical test software intended to be run on the CPU unit. It is implemented in Python using the GTK 3 GUI toolkit.

The sources and an installation script can be found under src/software/fpga_observer/ in the Cryring_BPM_HDL_Code_new Git repository.

Connect to the CPU unit e.g. via ssh. Clone the Cryring_BPM_HDL_Code_new Git repository:

git clone git@git.gsi.de:BEA_HDL/Cryring_BPM_HDL_Code_new.git

Install the PCIe driver:

cd src/software/pcie_driver
sudo ./install.sh

Install the FPGA Observer software:

cd ../fpga_observer
sudo ./install.sh

For the PCIe driver to work, the bitstreams of the FPGAs have to be loaded before powering the CPU unit. If that is not the case, power cycle the CPU unit by pulling out the Hot Swap Handle and pushing it in again. A software reboot does not work.

Connect to the CPU unit e.g. via ssh -X in order to allow a graphical connection. Start the FPGA Observer software by:

fpga_observer

A GUI should open and a choice of FPGA serial numbers should be displayed on the upper left corner. If the list is empty, either the loading of the FPGAs finished after powering the CPU unit or the PCIe driver did not install correctly. The FPGA serial numbers can be used to identify the AFC board you like to access. Choose a serial number and click connect.

The names and widths of the registers are read from an information memory region in the FPGA (see chapter 8.2.2). The status registers are displayed on the left and the configuration registers on the right.
The read button reads all the status registers either once or continuously if the continuous check button is checked. The write button writes all the configuration registers whose check buttons next to the write value are checked.

<b>Figure 9.1:</b> FPGA Observer - Register Access tab

The names and widths of the signals connected to the eight observer multiplexer inputs are read from an information memory region in the FPGA (see chapter 8.2.1).
The two combo boxes Observer 0 and Observer 1 determine which multiplexer inputs are selected for data acquisition. The combo box Trigger determines on which of the observer inputs the trigger will listen.
The Number Of Samples entry determines how many samples will be stored after a trigger event when the capture button has been pressed. If the continuous check button is checked, the trigger will be rearmed automatically when the data acquisition completes.

The individual Trigger Active (&) check buttons define on which signals the trigger will listen. All of the enabled conditions have to become true for a trigger event.
The trigger conditions for t = -1 and t = 0 contain the compare vectors of the two stage trigger which have to match in consecutive clock cycles. The Trigger Mask (&) defines on which bits of a signal the trigger will listen.

<b>Figure 9.2:</b> FPGA Observer - Data Acquisition tab

When the data acquisition completes, the open source waveform viewer GTKWave is called to display the captured data, which has been stored to a .vcd file before.

<b>Figure 9.3:</b> GTKWave

The result of the BPM algorithm and of the averaging are displayed in this tab. If the read button is pressed, the values from status registers 0 - 3 and 4 - 7 (see chapter 7.2.2) are read once (or continuously if the check button continuous is checked). The displayed values are the register values divided by $`2^{15}`$.

<b>Figure 9.4:</b> FPGA Observer - BPM Calculation tab

A configuration file with a special syntax can be loaded to configure the different peripheral devices documented in chapter 3. An initial configuration is already performed by the gateware after startup.

<b>Figure 9.5:</b> FPGA Observer - Peripherals Configuration tab

Information about the gateware version is displayed in this tab. The URL of the remote server of the Git repository, the latest commit hash and the latest commit date are read from an information memory region in the FPGA (see chapter 8.2.3). The bitstream generation date is read from status register 126 ’build timestamp’.

<b>Figure 9.6:</b> FPGA Observer - Gateware Information tab

There is a PCIe access test script under src/software/pcie_driver/test_pcie_access.sh in the Cryring_BPM_HDL_Code_new Git repository. It uses the tools provided together with the XDMA PCIe driver to test some basic reading and writing to different memories via the PCIe driver. The reading results are displayed via hexdump.

There is a script src/scripts/beautify_vhdl.py for autoformatting VHDL files using the open source software Emacs.

The script expects one parameter: <file that shall be formatted>, or all for formatting all VHDL files in the repository. The formatting is performed in place, overwriting the original source file.

The script applies several corrections and changes to the Emacs formatting result:

• correction of the handling of the comparison operator <=
• correction of the handling of initializations like (others => ’0’)
• enforcing of spaces around the operators +, -, *, /, &
• no indentation for closing brackets
• aligning of full comment lines to the indentation level of the following VHDL command
• indentation with tabs instead of spaces

Whenever the bitstream of an FPGA is reloaded, the CPU unit has to be rebooted via its Hot Swap Handle in order to establish a PCIe connection. A software reboot does not work.

An alternative possibility of remote power cycling the CPU unit is via the MCH.

The script src/scripts/powercycle_cpu_unit.py instructs the MCH via SSH to power down and repower the CPU unit. The script expects one parameter: <name of MCH, e.g. sdmch023>.

The script takes about 60 seconds to complete.

The script src/scripts/plot_frequency_response.py can be used to plot measurement data. It was used to create figure 12.4.

The monitoring and control configuration of the gateware is defined by the configuration files observer_signals.csv, read_registers.csv and write_registers.csv in the folder src/config.

The script src/scripts/generate_monitoring_and_control.py is used to convert the configuration to a VHDL file stored as src/vhdl/generated_constant_package.vhd. It contains the register default values and a Block RAM initialization vector containing the observer and register configuration.

The script is also executed by the gateware build flow documented in chapter 5.

There is a script doc/scripts/create_pdf.sh for generating a PDF file from the Latex sources in doc/tex. It calls the open source software Pdflatex twice on the top level documentation file Cryring_BPM_Gateware_Documentation.tex to enable the generation of references inside the PDF file.

There is a script doc/scripts/create_markdown.py for generating the Markdown file README.md in the root folder of the repository which is displayed on Gitlab’s start page for the repository. The script uses the open source software Pandoc for an initial conversion of the Latex sources in doc/tex.

The result of Pandoc is postprocessed for multiple reasons:

• conversion of the math syntax to Gitlab’s .md format
• corrections of the bibliography, HTML syntax and Latex labels
• corrections of the references to figures, tables and equations
• enumeration of chapters, sections and subsections
• adding of captions for figures and equations
• enumeration of figures, tables and equations
• generation of a table of contents
• implementation of citations

Additional documentation which is not included in the Latex sources is appended from the file doc/markdown/epilog.md.

Before being able to access the FPGA you need to program the JTAG switch on the AFC board using a script from the Cryring_BPM_HDL_Code_new Git repository. Open the Vivado Hardware Manager software:

Tools Run Tcl Script: src/scripts/program_scansta_jtag_switch.tcl

You should now see a xc7a200t_0 device.
Right click on it and choose Program Device.
Choose the correct bitstream (.bit file) and press OK. The programming takes about one minute.

If there is a JTAG Switch Module (JSM) in the MicroTCA crate, the bitstream can also be programmed remotely via a so called Xilinx Virtual Cable:

• download svf_to_nsvf-linux-x86.bin from MCH GUI JSM
• download afc_scansta.sfv from https://github.com/lnls-dig/fpga-programming
• convert afc_scansta.sfv to afc_scansta.nsfv using the command ./svf_to_nsvf-linux-x86.bin afc_scansta.sfv
• upload afc_scansta.nsfv in MCH GUI JSM to the port of the JTAG switch to which the AFC board you want to program is connected
• open Vivado Hardware Manager
• Open Target New Target Next Local Server Add Xilinx Virtual Cable (XVC)
• Hostname: sdmch<xxx>.acc.gsi.de
• Port: find correct port number in NAT-MCH GUI JSM
• Finish
• Open target
• you should see the FPGA now in Vivado Hardware Manager and can program it

The first four steps are persistent and only have to be executed initially.

There is a 256 MB SPI Flash memory on the AFCv3.1 board for persistent bitstream storage.

First you have to convert the bitstream (.bit) file to a .mcs file. There is a script in the Cryring_BPM_HDL_Code_new Git repository for this purpose:

src/scripts/convert_bit_to_mcs.sh <path to .bit file>

The .mcs file will be generated in the same folder as the .bit file.

Program the JTAG switch on the AFC board as described in chapter 11.1.1. You should now see a xc7a200t_0 device.
Right click on it and choose Add Configuration Memory Device and choose mt25ql256-spi-x1_x2_x4

You should now see a mt25ql256-spi-x1_x2_x4 device.

Right click on it and choose Program Configuration Memory Device.
Choose the .mcs file you created before and press OK. The programming is really slow and can take up to half an hour.

MCH global parameter SSH access: enabled
This will trigger SSH key generation which takes some minutes to complete.

PCIe parameter Upstream slot power up delay: 5 sec
Delay before the CPU unit will power up on start up. For making sure that the bitstreams are loaded to the AFC’s FPGAs from Flash memory before the CPU unit boots you might have to increase this value.

PCIe parameter PCIe hot plug delay for AMCs: 0 sec
Delay before the AFC boards will power up on start up.

Set the CPU-Unit as upstream AMC source in ’Virtual Switch 0’:

PCIe Virtual Switches Upstream AMC: AMC1/4..7
(for CPU unit in AMC slot 1)

Make sure you enable PCIe downstream ’4..7’ for the AMC slots which contain your AFC boards.

The most comfortable way of configuring the MCH is via its web interface. If you have accidentally disabled the webserver, set an invalid IP or DHCP configuration or reset the MCH settings to default, you can access the MCH via an USB connection to the micro USB port on the left side of the front panel.

On a Linux PC, connect a micro USB cable and check via dmesg that a LUFA USB-RS232 Adapter has been detected. The driver will be accessible at /dev/ttyACM<some number>, use e.g. Putty to connect to this serial port using the parameter speed = 19200.

Now typing mch will output information about the MCH. Typing ? will display a list of available commands. Most of the settings of the web interface are also available on the command line interface. You can for example set the IP address or a DHCP name to be able to connect to the web interface.

For programming the MMC firmware into the LPC microcontroller you need to install a proprietary software from NXP called LPCxpresso.

Download LPCxpresso from the NXP website [10]. You need to register for the download. Follow the instructions in INSTALL.txt. After the installation, open the IDE via <installation directory>/lpcxpresso and register the installation via Help Activate Create serial number and register (Free Edition). Create a serial number in the dialog, copy it to the form in the website and afterwards paste the activation key you got from the website to Help Activate Activate (Free Edition).

Disconnect the AFC board completely. The power for programming the microcontroller will come from the LPC-Link programmer. Connect and power the LPC-Link programmer via USB and connect the customized cable to the CPU-JTAG connector on the AFC board. Connect the plug so that the flat cable is pointing in the direction of the FMC connector.

Program the device via:

lpcxpresso/bin/dfu-util -d 0x0471:0xdf55 -c 0 -t 2048 -R -D lpcxpresso/bin/LPCXpressoWIN.enc

sudo lpcxpresso/bin/crt_emu_cm3_nxp -pLPC1768 -g -wire=winusb -load-base=0 -flash-load-exec=<path to firmware binary>

You can find the openMMC firmware binary under firmware/openMMC-full-afc-bpm-v1.4.0.bin in the Cryring_BPM_HDL_Code_new Git repository.

The FMC ADC boards were originally designed for very high input frequencies and are equipped with input filters that show a pronounced high pass characteristic.

<b>Figure 12.1:</b> Schematics of the original ADC input filter. Image taken from [11]

The part labeled TR1B BD0205F5050A00 is a balun with an operating range of 70 - 1000 MHz [12]. Lower frequencies are severely attenuated.
For being able to use the FMC ADC boards in the Cryring BPM system, the baluns have to be replaced by more suitable components.

Two approaches have been implemented (probably by Piotr Miedzik):

1. each balun is replaced by two wires
2. each balun is replaced by two capacitors of probably 100 nF (hint in an old email)

<b>Figure 12.2:</b> ADC input filter: balun <i>TR1B</i> replaced by two wires

<b>Figure 12.3:</b> ADC input filter: balun <i>TR1B</i> replaced by two capacitors

The heatspreader under the bottom of the FMC ADC board has to be unscrewed to access the baluns.

<b>Figure 12.4:</b> Magnitude frequency responses of different ADC input filters

Figure 12.4 shows the magnitude frequency responses of the original input filter and of the two modifications. The diagram data was created by using a sine signal from a signal generator with an amplitude of 2 $`V_{pp}`$ and by measuring the maximum amplitude swing of the raw ADC data.

[1] A. Reiter, R. Singh: Comparison of beam position calculation methods for application in digital acquisition systems. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, February 2018, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Paper_BPM_Algorithm.pdf

[2] P. Miedzik, H. Bräuning, T. Hoffmann, A. Reiter, R. Singh: A MicroTCA based beam position monitoring system at CRYRING@ESR. 16th Int. Conf. on Accelerator and Large Experimental Control Systems, Barcelona, Spain, October 2017, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Paper_BPM_architecture.pdf

[3] A. Reiter, W. Kaufmann, R. Singh, P. Miedzik, T. Hoffmann, H. Bräuning: The CRYRING BPM cookbook, March 2015, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Cryring_BPM_System_Overview.pdf

[4] AMC FMC Carrier (AFC) Git repository, Open Hardware Repository, https://ohwr.org/project/afc/wikis/home

[5] Silicon Labs: Timing part decoder web page, https://www.silabs.com/timing/lookup-customize

[6] Silicon Labs: Si571 datasheet, https://www.silabs.com/documents/public/data-sheets/si570.pdf

[7] Analog Devices: AD9510 datasheet, https://www.analog.com/media/en/technical-documentation/data-sheets/AD9510.pdf

[8] Renesas: ISLA216P datasheet, https://www.renesas.com/us/en/www/doc/datasheet/isla216p.pdf

[9] AFC v3.1 schematics, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Schematics_AFC_v3.1.pdf

[10] NXP: LPCxpresso download web page, https://www.nxp.com/design/microcontrollers-developer-resources/lpc-microcontroller-utilities/lpcxpresso-ide-v8-2-2:LPCXPRESSO

[11] FMC ADC 250M 16B 4ch schematics, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Schematics_FMC_ADC_250M_16B_4ch.pdf

[12] Anaren: Balun BD0205F5050A00 datasheet, https://git.gsi.de/BEA_HDL/datasheets/-/blob/master/Balun_BD0205F5050A00_datasheet.pdf

block diagram

Xilinx Vivado 2019.2 or 2017.4

Set your preferred Vivado version in src/config/project_config.sh.

The IPs are currently only maintained for Vivado 2019.2.

If you intend to use the Vivado GUI proceed as follows:

• open Vivado GUI
• use the TCL console in the bottom of the GUI to navigate to src/scripts using the commands pwd and cd
• type source create_project.tcl in the TCL console, this will set up a Vivado project and start the bitstream generation

There is one generated VHDL file src/vhdl/generated_constant_package.vhd which is generated by the script src/scripts/generate_monitoring_and_control.py. TODO: This script is designed to be run on Linux, create a script that is able to run on Windows.

• navigate to the root folder of the repository in a terminal
• type run/create_project.sh

This will open the Vivado GUI and set up a project, which can take some minutes.
The project will be generated in the folder output/<Vivado version>/project.

For a completely automatic script based build flow without using the Vivado GUI proceed as follows:

• navigate to the root folder of the repository in a terminal
• type run/run_build_flow.sh

A project will be generated in the folder output/<Vivado version>/build_flow.
The bitstream (if successful) will be generated in the subfolder aft_top.runs/impl_1.

• click on “Run Simulation” in the Vivado GUI (prerequisite: existing project → Vivado GUI based build flow)

The SDRAM interface IP starts needs an initial calibration process which finishes after about 120 us. The simulation time should be longer than that to see the actual system behavior, e.g. 200 us.

• navigate to the root folder of the repository in a terminal
• type run/run_simulation.sh
• you will find the output files of the simulation in the folder output/<Vivado version>/simulation.

Both boards carry 2 GiBytes of DDR3-SDRAM, divided in four modules of 512 MiBytes each.
The SDRAM model can be determined via the FBGA code printed on the modules using Micron FBGA and Component Marking Decoder.

• FBGA code: D9PBC, translates to Micron MT41J512M8RA-125:D
• operates at 1.5 V

• FBGA code: D9QBV, translates to Micron MT41K512M8RH-125 IT:E
• compatible to older MT41J family, operates at 1.5 V or 1.35 V

The ‘LD1’ (v1.0) or ‘STATUS’ (v1.2 and v2.3) LED on the right of the FMC board front panel is connected differently between v1.0 and (v1.2 and v2.3). When using the location constraints for v1.2 and v2.3 together with a v1.0 board, the LED lights as follows:

wanted red → off
wanted green → lights green
wanted blue → lights red

Besides that, there seem to be no differences in the connections to the FPGA.

The gross data rate of the SDRAM interface is 800 MT/s with 32 bits/transfer, resulting in a theoretical gross data rate of 3.2 GiBytes/s. The maximum achievable data rate is limited by concurrent read and write accesses and by SDRAM refresh cycles. A permanent write data rate of 2 GiBytes/s has been tested, enabling the storage of the samples of all eight ADCs:
125 MT/s * 16 bits/transfer * 8 = 2 GiBytes/s
The SDRAM capacity of 2 GiBytes is sufficient to store the stream data of all eight ADCs for 1 second.

In the FPGA design there are configurable input delay modules for the clock and for the data input pins. By increasing the input delay of either a clock or of the associated data inputs, the alignment can be corrected in both directions. The input delays provide a 32 tap delay line with a configurable delay between 0 to 31 taps.

TODO: Find a data sheet which provides the delay time of one tap.

The ADCs offers programmable user patterns that can be sent in place of the ADC samples to check the correct timing of the digital interface.
For finding the optimum delay values, the following procedure is applied:

• The clock input delay is increased until the pattern begins to deteriorate and the delay index at which that happens is noted.
• After that the clock input delay is reset to 0 and the data delay is increased until the pattern begins to deteriorate.
• The optimum value is assumed to be the midpoint between these values.

For an ADC clock frequency of 125 MHz the result is:

FMC0: no deterioration at clock delay 0x1f but at data delay 0x06 →

• ADC clock delay value: 0x0D
• ADC data delay value: 0x00

FMC1: no deterioration at clock delay 0x1f but at data delay 0x05 →

• ADC clock delay value: 0x0D
• ADC data delay value: 0x00

run cd src/software/pcie_dma_driver

run ./customize.sh

this will: * install Git * install development tools needed for building kernel modules * clone the Xilinx PCIe DMA driver Git repository

run sudo ./install_pcie_dma_kernel_module.sh

You can find additional documentation in a README file in the Xilinx PCIe DMA driver Git repository:

‘dma_ip_drivers/XDMA/linux-kernel/readme.txt’

run cd src/software/fpga_observer

run ./install.sh.

fpga_observer will start a GUI providing monitoring and controlling features for the FPGA gateware.
The raw monitoring data can be stored to a binary file, described in Reading data from SDRAM on AFC board to a file.
The observer software converts the binary .bin file to a .vcd file which can be read in waveform viewers like GTKWave.

GTKWave is available in the EPEL packet sources for CentOS 7. Install it with:

sudo yum install https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm

sudo yum install gtkwave

Copy ‘.gtkwaverc’ to your home directory for disabling GTKWave’s splash screen:

cp gtkwave_settings/.gtkwaverc ~

Run GTKWave:

gtkwave gtkwave_settings/wave_config.gtkw <path to .vcd file>

The file ‘gtkwave_settings/wave_config.gtkw’ contains information about how the waves shall be displayed, like signals to display, radices, etc.

After loading the bitstream to the FPGA on the AFC board, the CPU unit has to be rebooted by pulling its hot swap handle out and pushing it in again. A Linux reboot via ‘sudo reboot’ does NOT work, this will disable the PCIe connection to the AFC board.

TODO: Find the reasons for that behaviour, maybe it has something to do with the BIOS settings or with the MCH PCIe settings.

This behaviour does not occur with the LNLS 100 MHz design, which survives a Linux soft reboot. The 100 MHz design does not even need a reboot, since its PCIe driver works directly after programming the bitstream (different from the Xilinx XDMA driver).

TODO: Check for differences in the settings of the PCIe Xilinx IP cores. LNLS’s 100 MHz design uses ‘7 Series Integrated Block for PCI Express’ which seems to be a subset of ‘DMA/Bridge Subsystem for PCI Express’ used in this design and in Piotr Miedzik’s design.

The CPU unit can also be shut down and started again via the command line interface of the MCH:

Connect to the MCH via ssh root@sdmch<MCH number>. The password is ‘nat’.

show_fru will show you the FRU numbers of the AFC slots. Look up the FRU number of the CPU unit.

shutdown <FRU number> will power down the CPU unit.

fru_start <FRU number> will start the CPU unit.

The script powercylce_cpu_unit.sh in this repository performs the commands above. It requires one argument: IP or URL of the MCH.
You might have to adapt the FRU number in the script to your needs, depending on the location of the CPU unit.

Install necessary packages and get the driver’s source code:

src/software/PCIe_DMA_driver/customize.sh

Build and load the driver:

src/software/PCIe_DMA_driver/install_pcie_dma_kernel_module.sh

The driver can be loaded again (e.g. after a reboot) by sudo modprobe xdma or by sudo XDMA/linux-kernel/tests/load_driver.sh.

Example for reading 4096 bytes of data from address 0x00000000:

sudo XDMA/linux-kernel/tools/dma_from_device -a 0 -s 4096 -o 0 -c 1 -f ~/test_memory_read.bin

The output file is of a binary format which you can display with

hexdump -C test_memory_read.bin

Reading the whole SDRAM content (2 GiB) to a file on the CPU-Unit’s hard disk takes about 17 seconds.

cd ~ && mkdir ramdisk && sudo mount -t tmpfs -o size=2G none ramdisk && cd -

Now the reading of the whole SDRAM content takes about 5 seconds:

sudo XDMA/linux-kernel/tools/dma_from_device -a 0 -s 2147483648 -o 0 -c 1 -f ~/ramdisk/test_memory_read.bin

The clock frequency of the input clock to the PCIe IP core is different between the MMC firmwares of Creotech and LNLS:

PCIE_CLK1_C (name on AFC schematic): 125 MHz (Creotech), 100 MHz (LNLS)

There is a setting ‘Reference Clock Frequency’ in the Xilinx ‘DMA/Bridge Subsystem for PCI Express’ IP core.
At the moment it is set to 125 MHz to support Creotech’s original MMC firmware.

To make this design work with LNLS’s MMC firmware, the setting has to be changed to 100 MHz.

There are two tricolor LEDs connected to FPGA pins:

• ‘L3’ in the center of the AFC board front panel
• ‘LD1’ (v1.0) or ‘STATUS’ (v1.2) on the right of the FMC board front panel

Each tricolor LED consists of three independent LEDs (red, green and blue).

In Service (‘L1’, green)
Alarm (‘L2’, red)
Hot Swap (‘HS’, blue)

Insertion of AFC board:

Removal of AFC board:

Source: NXP

Source: NAT-MCH HUB-Module PCIe –Technical Reference Manual

• Use git clone to get the recent application code, otherwise the pipelines might fail during git fetch.
  

Settings → CI / CD → General pipelines → Git strategy for pipelines: git clone

• Increase timeout to allow FPGA build to finish.
  

Settings → CI / CD → General pipelines → Timeout: 6h

Core i5-8500, 2018, 6 cores / 6 threads, 3.0 - 4.1 GHz, CPU Mark: (11830 MT, 2405 ST), 32 GB RAM, SSD

• simulation: 00:05:20 h
• FPGA build: 01:16:17 h

Xeon W3505, 2009, 2 cores / 2 threads, 2.53 GHz, CPU Mark: (1842 MT, 1052 ST), 24 GB RAM, HDD

• simulation: 00:14:16 h
• FPGA build: 02:54:53 h

JTAG Device

Creotechs MMC firmware routes a 125 MHz clock to the PCIe reference clock input, whereas LNLS’s Open MMC firmware routes a 100 MHz clock to this pin.
The frequency of sys_clk is 125 MHz for both.
The Open MMC firmware forwards the signal of the reset button on the front panel to the FPGA pin AG26 after some seconds. Additionally, other operations seem to be performed since the PCIe connection to all FMC boards breaks. It is unclear if or how Creotechs MMC firmware handles reset button actions, since there is no observable reaction.

This gateware design is currently functional for the Creotech MMC firmware. For running it together with the Open MMC firmware, the PCIe reference clock frequency in the IP ‘pcie_dma_ip’ has to be changed to 100 MHz.

The ‘xmda’ PCIe driver enumerates the detected PCIe connections randomly starting with ’/dev/xdma0*’. In order to determine which AFC board is linked to which instance number, it is helpful to read the FPGA serial number, which consists of 57 bits. In this design the FPGA serial number is stored in read register 127.