This shows you the differences between two versions of the page.
Both sides previous revision Previous revision Next revision | Previous revision | ||
projects:maps:mapsadapter:rahmenpulsmodul:overview [2020/01/31 17:10] carsten [The realized signal flow through the for IO-connectors of PXI-7811R is:] |
projects:maps:mapsadapter:rahmenpulsmodul:overview [2020/02/03 10:53] (current) carsten [Internal pictures] |
||
---|---|---|---|
Line 1: | Line 1: | ||
+ | ☚ [[projects: | ||
+ | |||
====== Rahmenpuls-Modul ====== | ====== Rahmenpuls-Modul ====== | ||
===== The realized signal flow through the for IO-connectors of PXI-7811R is: ===== | ===== The realized signal flow through the for IO-connectors of PXI-7811R is: ===== | ||
- | {{: | + | This differs from the flow suggestion made in diploma theses from M. Larrousis, but is conncerted with programmers. Reason for that is to clear seperate yellow signals " |
+ | |||
+ | {{: | ||
- | This differs from the flow suggestion made in diploma theses from M. Larrousis, but is conncerted with programmers. Reaon for that is to clear seperate yellow signals " | + | Yellow inputs receive " |
+ | |||
+ | To get an impression see folowing Dokument for UNILAC-Timing zones (Thanks to C.Andre): | ||
+ | |||
+ | The idaer shout be to combine all those AC-transformators inside the same time zone at same ADCs for being sampled from the same trigger! | ||
===== Designated Diploma Signal Flow to NI-FPGA " | ===== Designated Diploma Signal Flow to NI-FPGA " | ||
- | Old setup:\\ | + | Old setup: |
- | {{: | + | {{: |
- | Realized ports for Rahmenpulse (There are only 40 usable signal lines per cable): | + | ===== Physical Realization |
- | {{: | + | There are only 40 usable signal lines per cable\\ |
+ | |||
+ | {{: | ||
===== Boards ===== | ===== Boards ===== | ||
Line 24: | Line 35: | ||
[[projects: | [[projects: | ||
- | [[projects: | + | [[projects: |
===== Internal pictures ===== | ===== Internal pictures ===== | ||
Line 31: | Line 42: | ||
{{ : | {{ : | ||
+ | |||
+ | ===== Infos zu Trafos und Timing ===== | ||
+ | |||
+ | [[projects-internal: | ||
+ | |||
+ | ---- | ||
+ | ☚ [[projects: |