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projects:maps:mapsadapter:rahmenpulsmodul:overview [2020/01/31 17:02] carsten [Designated Diploma Signal Flow to NI-FPGA NI87xx] |
projects:maps:mapsadapter:rahmenpulsmodul:overview [2020/02/03 10:53] (current) carsten [Internal pictures] |
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====== Rahmenpuls-Modul ====== | ====== Rahmenpuls-Modul ====== | ||
- | ===== Designated Diploma Signal Flow to NI-FPGA " | + | ===== The realized signal flow through the for IO-connectors of PXI-7811R is: ===== |
- | The realized signal flow through | + | This differs from the flow suggestion made in diploma theses from M. Larrousis, but is conncerted with programmers. Reason |
- | {{ : | + | {{: |
- | This differs from the flow suggestion made in diploma theses from M. Larrousis but is conncerted with programmers. reaon for that is to clear seperate yellow signals | + | Yellow inputs receive |
- | Old setup: | + | To get an impression see folowing Dokument for UNILAC-Timing zones (Thanks to C.Andre): {{ : |
- | {{ : | + | The idaer shout be to combine all those AC-transformators inside the same time zone at same ADCs for being sampled from the same trigger! |
- | Realized ports for Rahmenpulse (There are only 40 usable signal lines per cable): | + | ===== Designated Diploma Signal Flow to NI-FPGA " |
- | {{ : | + | Old setup: Here the designated signal distribution does not face the two different signal sources which has to be reached which one cable each! |
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+ | {{: | ||
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+ | ===== Physical Realization : ===== | ||
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+ | There are only 40 usable signal lines per cable\\ | ||
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+ | {{: | ||
===== Boards ===== | ===== Boards ===== | ||
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[[projects: | [[projects: | ||
- | [[projects: | + | [[projects: |
===== Internal pictures ===== | ===== Internal pictures ===== | ||
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{{ : | {{ : | ||
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+ | ===== Infos zu Trafos und Timing ===== | ||
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+ | [[projects-internal: | ||
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+ | ---- | ||
+ | ☚ [[projects: |