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☚ [[instruments:overview#macro_pulse_selector_maps|Instrumenten-Übersicht]] ★ <color white/white>#######################</color> ★ [[projects:maps21:maps21|MAPS-2021]] ★<color white/white>#######################</color> ★ [[fair-bd:daq:documentation:new_maps|New MAPS-DAQ-Hardwareinfo]] ☛
 
The MAPS modernization is a long-term activity, yet unfinished.

<color #ed1c24> **Warning: the wiki pages below refer to an intermediate development step, which was never set into operation!! ** </color>

For up-to-date information of the now restarted MAPS modernization project follow the link New MAPS info above!!


====== MAPS System Overview (INTERMEDIATE STEP!) ======

| {{ :projects:maps:wasmitwem.jpg?direct&600 |}}  | {{ :projects:maps:sei2005-maps.ppt |Präsentation M. Laroussi}}\\ \\ **Schwarz**: MAPS-System in Kontrollsystem\\ <color blue>**Blau**</color>: Neues MAPS-System\\ \\ [[projects:maps:digitizer|BCT digitizer]]\\ [[projects-internal:uni-bcts:ov-uni-bcts|Trafos und Timing]] ☛  |  2005   ---- Plan ----> 2012\\ {{:projects:maps:maps-uebersicht.png?direct&600|MAPS-Übersicht 2005->}}   |

The "**M****a**cro**P**ulse**S**elector" system was built to display analog signals of UNILAC beam current transformers (BCT), as an addition to the already established beam current readout (for average macro-pulse currents) via the GSI control system. It utilizes a client-server architecture. The DAQ and server hardware run on a NI-PXI crate under LabView® RT. One or more users can choose two or more out of up to 128 BCT signals for the display by the client software. 
The project was initiated by A. Peters (former SD-group head) in 2005 and developped by M. Laroussi (diploma graduation work), Dr. H. Brandt (GSI EE, server software), M. Hartung (GSI SD, client software), and M. Kümmerling (Hörmann-IMG GmbH, MAPS interfaces, SerDes hardware, PXI interfaces) .

^  Real physical layout inside 19"-rack  ^  Description modules top down  ^
|{{:projects:maps:maps-rack.jpg?direct&600|Das MAPS-Rack}}\\ <color white/white>###################################################</color>  | 1.) Test-PC (Top of Rack)\\ \\ 2.) **[[projects:maps:mapsadapter:overview|  MAPS-Adapter]]** consisting of "[[projects:maps:mapsadapter:analogsignalmodul:overview|Analogue signal module]]" (6H below, half equipped) and "[[projects:maps:mapsadapter:rahmenpulsmodul:overview|Rahmenpulsmodul]]"  This adpter collects on it's rear panel:\\ * up to 128 BNC analogue signals, feeding them via 8 NI multi-line-cables on the front to 8 NI ADC boards with eight channel each.\\ * 8x Backside inputs LEMO 00 and 8x Monitor outputs on front for Timing signals to be fet to NI-ADCs: Here the saple window is given to the ADC: can be fet chooseable ((Hardare)) to one of eight "Programmable Timing Inputs on board and backplane (PFI0..7). \\ \\ 3.) [[projects:maps:mapsadapter:rahmenpulsmodul:overview|Rahmenpulsmodul]]: collects Timing signals from "Digitizers" moduls: This moduls sample Trafo signals for existing control system. Trafos Analog signals and Timing to that modul are then passed to additional new MAPS system\\ \\ 4.) [[projects:maps:niequippment|NI-PXI Crate]]\\ * Houses 8x ADC-boards for digitizing the analog signals and\\ * 1x PXI7811 FPGA board to extract informations about beam properties (ACC no., gate pulse duration, status) from MAPS bus\\ \\ 5.) [[projects:maps:T-test7811|T-Test7811]]: Three modules in 19" frame: Only indroduced if signals between one of two signal sources if signals inside collecting cable are to be meassured. Pass out of signals for measuring purpose (Oszzi)  \\ \\ 6.) [[projects:maps:mapsinterface|MAPS-Bus-Interface:]] \\ This is the modul in 3U 19" frame connected with the red cable: interface extracts informations of actual virtual accelarators from MAPS-bus to pass it to NI-crate\\ \\ 7.) Timing box  \\ creates general timing gate pulses (50 Hz start trigger, EOC) passed to leftmost adapter (front panel) in MAPS adapter. Shown modul is the receiver and of course there is although an sender to that. | 

The actual sources of analog signals and gate pulses ("Rahmenpulse") are the [[projects:maps:digitizer|BCT digitizer]] modules.

Currently only half of the DAQ system is eatablished (64 from 128 possible BCT channels). The fully extented state is schematically shown here. 16 (grey) cables are equipped with 68-pin 0.050 D-Type connectors at both ends, and carry the analogue BCT signals to the ADC-boards. 4 black cables with VHDCI 68-pin male type connectors on the FPGA side and 68-pin 0.050 D-Type on the other end carry gate pulses ("Rahmenpulse") to the FPGA board:

{{:projects:maps:gesamtsystem.jpg?nolink&600 | MAPS-Adapter connections schematics}}

[[projects:maps:diplomthesis|Diploma Thesis from Mohammed Laaroussi]]

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☚ [[instruments:overview#macro_pulse_selector_maps|Instrumenten Übersicht]] ★ <color white/white>##########################################</color>★ [[fair-bd:daq:documentation:new_maps|New MAPS info]] ☛
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