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ds:software:hdl [2016/02/08 10:26]
pmiedzik [FMC] 		ds:software:hdl [2016/07/12 13:07] (current)
pmiedzik [Register description]
Line 5: Line 5:
 | 1 |  ''000000000000ce42'' | ''ff07fc47'' | ''0x1000'' | WR-Periph-Syscon | | 1 |  ''000000000000ce42'' | ''ff07fc47'' | ''0x1000'' | WR-Periph-Syscon |
 | 2 |  ''000000000000ce42'' | ''e2d13d04'' | ''0x2000'' | WR-Periph-UART | | 2 |  ''000000000000ce42'' | ''e2d13d04'' | ''0x2000'' | WR-Periph-UART |
-| 3 |  ''000000000000ce42'' | ''779c5443'' | ''0x3000'' | WR-Periph-1Wire | +| 3 |  ''000000000000ce42'' | ''779c5443'' | ''0x3000'' | WB-OneWire-Master | 
-| 4 |  ''000000000000a8df'' | ''441c5145'' | ''0x4000'' | [[ds:software:hdl#wb_gpio_raw|WB-GPIO-RAW]] |+| 4 |  ''0000000000000651'' | ''eef0b198'' | ''0x2000'' | WB4-Bridge-GSI | 
 +| 4.1 |  ''000000000000ce42'' | ''123c5443'' | ''0x3000'' | WB-I2C-Master | 
 +| 4.2 |  ''000000000000ce42'' | ''779c5443'' | ''0x3100'' | WB-OneWire-Master | 
 +| 4.3 |  ''000000000000a8df'' | ''441c5145'' | ''0x3200'' | [[ds:software:hdl#wb_gpio_raw|WB-GPIO-RAW]] |
 | 5 |  ''000000000000a8df'' | ''441c5146'' | ''0x5000'' | [[ds:software:hdl#wb_scaler|WB-SCALER]] | | 5 |  ''000000000000a8df'' | ''441c5146'' | ''0x5000'' | [[ds:software:hdl#wb_scaler|WB-SCALER]] |
 +
 +
 +{{:ds:software:ipm_scaler_current.png?direct&500|Current design}}
 +
 +===== Final design =====
 +
 +FIXME
 +{{:ds:software:ipm_scaler.png?direct&300|Final design}}
 +===== Initialization =====
 +
 +  - configure inputs
 +    * direction (**WB-GPIO-RAW=>DDR**)
 +    * termination (**WB-GPIO-RAW=>TR**)
 +  - setup input map registers
 +    * **WB-SCALER=>CounterMap**
 +    * **WB-SCALER=>LatchMap**
 +    * **WB-SCALER=>StartStopMap**
 +  - reset all counters by writing 1 to **WB-SCALER=>SC** - **empty/reset** bit
 +  - enable scaler (optional) by writing 1 to **WB-SCALER=>SC** - **running/start** bit
 +
 +===== Data readout =====
 +
 +  - Check status register (**empty** bit) if new data is available 
 +  - Latch new data into circular buffer (**WB-SCALER=>OCounter**) by writing **load_fifo**  bit
 +  - Read **OCounter** register four times.
  
 ====== FMC ====== ====== FMC ======
  
 +  * repository: LOBI IP Cores
 +    * https://github.com/qermit/lobi-ip_cores
 +    * http://gitorious.gsi.de/lobi/lobi-ip_cores
 +  * repository: FMC HDL
 +    * https://github.com/qermit/fmc-hdl
 +    * http://gitorious.gsi.de/lobi/fmc-hdl
 ===== FMC Dio 5ch TTL ===== ===== FMC Dio 5ch TTL =====
  
Line 16: Line 50:
  
 ^ BusPath ^ VendorID ^ Product ^ BaseAddress(Hex) ^ Description ^ ^ BusPath ^ VendorID ^ Product ^ BaseAddress(Hex) ^ Description ^
-| 1 |  ''000000000000????'' | ''????????'' | ''0x????'' | WB4-Bridge-GSI | +| 1 |  ''000000000000????'' | ''????????'' | ''0x0000'' | WB4-Bridge-GSI | 
-| 2 |  ''000000000000????'' | ''????????'' | ''0x????'' | WR-Periph-1Wire | +| 2 |  ''000000000000????'' | ''????????'' | ''0x1000'' | WR-Periph-1Wire | 
-| 3 |  ''000000000000????'' | ''????????'' | ''0x????'' | WB-I2C-Master | +| 3 |  ''000000000000????'' | ''????????'' | ''0x1100'' | WB-I2C-Master | 
-| 4 |  ''000000000000????'' | ''????????'' | ''0x????'' | [[ds:software:hdl#wb_gpio_raw|WB-GPIO-RAW]] | +| 4 |  ''000000000000????'' | ''????????'' | ''0x1200'' | [[ds:software:hdl#wb_gpio_raw|WB-GPIO-RAW]] | 
-| 5 |  ''000000000000????'' | ''????????'' | ''0x????'' | [[ds:software:hdl#wb_scaler|WB-SCALER]] |+
  
  
Line 28: Line 62:
 ===== WB Scaler ===== ===== WB Scaler =====
    
-master_mode        => PIPELINED +  * master_mode        => PIPELINED 
- +  * master_granularity => WORD
-master_granularity => WORD+
  
 ==== Register map ===== ==== Register map =====
  
 ^ Register     ^ Address ^ Default Value ^ Description ^ ^ Register     ^ Address ^ Default Value ^ Description ^
-| SC             | **0b000    ** | 0x00000001 | Status and controll +| SC             | **0b000    ** | 0x00000001 | Status and control | 
-| Countermap     | **0b001    ** | 0x08040201 | +| CounterMap     | **0b001    ** | 0x08040201 | 
-| LatchMap       | **0b010    ** | 0x00000010 | +| LatchMap       | **0b010    ** | 0x00000010 | Bit 8 wired to software latch | 
-| StartStopMap   | **0b011    ** | 0x00000080 |+| StartStopMap   | **0b011    ** | 0x00000080 | Bit 8 wired to software start/stop |
 | CCounter       | **0b100    ** | 0x00000000 | | CCounter       | **0b100    ** | 0x00000000 |
 | LCounter       | **0b101    ** | 0x00000000 | | LCounter       | **0b101    ** | 0x00000000 |
Line 48: Line 81:
  
 ^ Bits ^ hex ^ Name ^ R/W ^ Description ^ ^ Bits ^ hex ^ Name ^ R/W ^ Description ^
-|  0 |  (0x01) | empty         |  rw  | +|  0 |  (0x01) | empty/reset    |  rw  | 
 |  1 | | full          |  r  |  |  1 | | full          |  r  | 
 |  2 | | threshold     |  r  |  |  2 | | threshold     |  r  | 
-|  3 |  (0x08) | running       |  rw  | +|  3 |  (0x08) | running/start       |  rw  | 
 |  4 |  (0x10) | stop          |  w  | |  4 |  (0x10) | stop          |  w  |
 |  5 |  (0x20) | load_current  |  w  | |  5 |  (0x20) | load_current  |  w  |
 |  6 |  (0x40) | load_fifo     |  w  | |  6 |  (0x40) | load_fifo     |  w  |
 +|  7 |  (0x80) | software_latch     |  w  |
 |  11 - 8 | | counter_ovf   |  r  | |  11 - 8 | | counter_ovf   |  r  |
 +|  12 | | load_current_auto |  rw  | FIXME |
  
  
-=== Countermap (0b001) ===+=== CounterMap (0b001) ===
  
 ^ Bits ^ Name ^ R/W ^ Description ^ ^ Bits ^ Name ^ R/W ^ Description ^
Line 70: Line 105:
   * g_master_mode        => CLASSIC   * g_master_mode        => CLASSIC
   * g_master_granularity => WORD   * g_master_granularity => WORD
 +
 +==== Register map ====
  
 ^ Register     ^ Address ^ Default Value ^ Description ^ ^ Register     ^ Address ^ Default Value ^ Description ^
-| CODR           | **0b000    ** | 0x00000000 | clear output register +| CODR           | **0b000    ** | 0x00000000 | clear output register | 
-| SODR           | **0b001    ** | 0x00000000 | set output register +| SODR           | **0b001    ** | 0x00000000 | set output register | 
-| DDR            | **0b010    ** | 0x00000000 | data direction register +| DDR            | **0b010    ** | 0x00000000 | data direction register | 
-| PSR            | **0b011    ** | 0x00000000 | pin state register +| PSR            | **0b011    ** | 0x00000000 | pin state register | 
-| TR             | **0b100    ** | 0x00000000 | termination register +| TR             | **0b100    ** | 0x00000000 | termination register | 
-| AFR            | **0b101    ** | 0x00000000 | alternative function register+| AFR            | **0b101    ** | 0x00000000 | alternative function register |
  
  
ds/software/hdl.1454923591.txt.gz · Last modified: 2016/02/08 10:26 by pmiedzik

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