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ds:projects:cryring:cups [2015/01/22 15:09] haraldbraeuning |
ds:projects:cryring:cups [2019/08/19 10:17] (current) haraldbraeuning |
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====== DAQ for CryRing Cups ====== | ====== DAQ for CryRing Cups ====== | ||
- | The cups in the [[fair-bd: | + | The cups in the [[fair-bd: |
- | The FESA class is designed to operated with DC beams as well as bunched beams. However, the preferred | + | The FESA class is designed to operated with DC beams as well as bunched beams. However, the preferred |
+ | |||
+ | |||
+ | ===== Hardware ===== | ||
+ | |||
+ | | VME crate | Elma VME 044-680 (8 slots) | sdvme014 | | | | ||
+ | | FEC | Men A20 | sddsc022 | | | | ||
+ | | Timing Receiver | Vetar 2a | | | | | ||
+ | | ADC | SIS3302 | 0x30000000 | channel 7 | YRT1DC2 | | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | | SIS3302 | 0x50000000 | channel 0 | YR01DC1 | | ||
+ | | | ||
+ | | | ||
+ | | | SIS3302 | 0x60000000 | channel 0 | YRE1DC1 (temporary) | | ||
+ | | I/O | SIS3820 32bit output register | 0x40000000 | bit 0-7 | YRT1DC2 | | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | | SIS3820 32bit output register | 0x40010000 | bit 0-7 | YR01DC1 | | ||
+ | | | ||
+ | | | ||
+ | | | SIS3601 32bit output register | 0x40020000 | bit 0-7 | YRE1DC1 (temporary) | | ||
+ | |||
+ | |||
+ | | FC COntrol Box | sdadev067.acc.gsi.de (140.181.137.178) | channel 0 | YRT1DC2 | | ||
+ | | | | channel 1 | YRT1DC3 | | ||
+ | | | | channel 2 | YRT1DC6 | | ||
+ | | | | channel 3 | YRT1DC7 | | ||
+ | | | | channel 4 | YR01DC1 | | ||
+ | | | | channel 5 | YR07DC2 | | ||
+ | | | | channel 6 | YR11DC3 | | ||
+ | | | | channel 8 | YRE1DC1 (temporary) | | ||
===== Documentation ===== | ===== Documentation ===== | ||
- | * {{: | + | * {{: |
* {{: | * {{: | ||
* {{: | * {{: |