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projects:maps21:s:dcont:code:pins2:pins2 [2024/05/07 10:56] carsten |
projects:maps21:s:dcont:code:pins2:pins2 [2024/09/17 09:48] (current) carsten [Pin-Mapping2] |
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+ | ☚ [[projects: | ||
+ | |||
====== Pin-Mapping2 ====== | ====== Pin-Mapping2 ====== | ||
+ | |||
+ | Zuletzt geholt am 17.9.2024 geschreiben am 9.7.2024: | ||
+ | |||
+ | %% | ||
+ | ==== aktuelle Version ==== | ||
<code vhdl> | <code vhdl> | ||
+ | # location constraints | ||
+ | |||
+ | net clk_0p001 loc = p32; | ||
+ | #net clk_10 | ||
+ | #net clk_10_n | ||
+ | |||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | </ | ||
+ | <color / | ||
+ | <code vhdl> | ||
+ | net rotary_switch< | ||
+ | net rotary_switch< | ||
+ | net rotary_switch< | ||
+ | |||
+ | net stroke< | ||
+ | net stroke< | ||
+ | net stroke< | ||
+ | net stroke< | ||
+ | net stroke< | ||
+ | |||
+ | net period< | ||
+ | net period< | ||
+ | net period< | ||
+ | net period< | ||
+ | net period< | ||
+ | net period< | ||
+ | |||
+ | net manual_range< | ||
+ | net manual_range< | ||
+ | net manual_range< | ||
+ | net manual_range< | ||
+ | |||
+ | net display_mode< | ||
+ | net display_mode< | ||
+ | net display_mode< | ||
+ | |||
+ | # LEDs : correct 180° rotation of display PCB for all columns and for rows 0 to 7 | ||
+ | # rows 8 and 9 not correctable due to pins not conntected to CPLD 1 => row 9 is located at the top | ||
+ | |||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | # rows 8 and 9 not correctable due to pins not conntected to CPLD 1 | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | |||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | # rows 8 and 9 not correctable due to pins not conntected to CPLD 1 | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | |||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | |||
+ | # timing constraints | ||
+ | |||
+ | net clk_0p001 period = 1000000; | ||
+ | #net clk_10 | ||
+ | #net clk_10_n | ||
+ | |||
+ | </ | ||
+ | |||
+ | ==== Vorversion ==== | ||
+ | |||
+ | p53 (DECODE) nicht gesetzt? | ||
+ | |||
+ | <code vhdl> | ||
+ | # location constraints | ||
+ | |||
+ | net clk_0p001 loc = p32; | ||
+ | #net clk_10 | ||
+ | #net clk_10_n | ||
+ | |||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | net clamp_pulses< | ||
+ | |||
+ | net rotary_switch< | ||
+ | net rotary_switch< | ||
+ | net rotary_switch< | ||
+ | |||
+ | net stroke< | ||
+ | net stroke< | ||
+ | net stroke< | ||
+ | net stroke< | ||
+ | net stroke< | ||
+ | |||
+ | net period< | ||
+ | net period< | ||
+ | net period< | ||
+ | net period< | ||
+ | net period< | ||
+ | net period< | ||
+ | |||
+ | net manual_range< | ||
+ | net manual_range< | ||
+ | net manual_range< | ||
+ | net manual_range< | ||
+ | |||
+ | net display_mode< | ||
+ | net display_mode< | ||
+ | net display_mode< | ||
+ | |||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | net led_rows_red< | ||
+ | |||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | net led_rows_green< | ||
+ | |||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | net led_columns< | ||
+ | |||
+ | # timing constraints | ||
+ | |||
+ | net clk_0p001 period = 1000000; | ||
+ | #net clk_10 | ||
+ | #net clk_10_n | ||
+ | |||
+ | |||
</ | </ |